COMP 409 Lecture Notes - Lecture 2: Context Switch, Kolmogorov Space, Floating-Point Unit
20 Mar 2018
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Requirement: must have 2 a"s or 2 b"s together (cid:314) this is not possible, unless done concurrently . Recall from last lecture: threads do, amdahl"s law (speedup is bounded) (expressiveness) Modern, super-scalar processor, pipelined, multi-issue (low level parallelism) 5: two flavors to access memory, uma (uniform memory access, all memory accesses cost the same (modulo the cache, note: our caches need to reflect the same view on memory. T0 r1 = x x = r1 + 1. = x (x now changed: caches need to be coherent (or consistent, numa (non-uma) (distributed system) Symmetric mp (smp) (cid:314) m. p: symmetric (cid:314) same cpus, smp"s (cid:314) physically separate cpus. All rights reserved: faster cache communication, disadvantage to cmp, smp, lots of programs are single-threaded, the chip (half of the cpus) are wasted . T3 fadd fadd fadd int/float ops: 1 cycle load: 2 cycles. Slot 1: t1. 1 add, t1. 3 add, t2 load, t2 add, t3 fadd, t3 fadd.
