CMPSC 64 Lecture Notes - Lecture 15: Intime
Document Summary
The result is that the output state is maintained even if the input changes. S = 0, r = 0 --> the circuit output holds memory of its prior value (state) Combining r and s inputs into one: the gated d latch. Force s and r inputs to always be opposite of each other. Make them the same as an input d (d = s, !d = r) Create a way to "gate" the d input. D input goes through only if an enable input e is 1. If e is 0, then hold the state of the previous state. Q remains the same when e = 0. Enabling the latch synchronously: the clocked d latch. If apply a synchronous clock on input e, you get a clocked d latch. A clock is an input that cycles from 1 to 0, then back to 1 again in a set time period.
