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Lecture 13

COMP 273 Lecture Notes - Lecture 13: Shift Register, Or Gate, The Selector


Department
Computer Science (Sci)
Course Code
COMP 273
Professor
Piotr Przytycki
Lecture
13

Page:
of 7
COMP 273 13 - MIPS datapath and control 1 Feb. 22, 2016
You are familiar with how MIPS programs step from one instruction to the next, and how
branches can occur conditionally or unconditionally. We next examine the machine level repre-
sentation of how MIPS goes from one instruction to the next. We will examine how each MIPS
instruction is “decoded” so that data is passed to the appropriate places (e.g. from register to
memory, from memory to a register, from a register to another register, etc). By the end of this
lecture and the next, you will have a basic understanding of how the combinational and sequential
circuits that you learned at the beginning of this course are related to the MIPS instructions and
programs that we have covered in more recent lectures.
Data paths for MIPS instructions
In this lecture and the next, we will assume that one instruction is executed in each clock cycle.
This is known as the single cycle model. In the lecture following the study break, we will see the
limitations of the single cycle model, and we will discuss how MIPS gets around it, namely by
”pipelining” the instructions.
Instruction fetch
Both data and instructions are in Memory. For an instruction to be executed, it first must be read
out of Memory. MIPS has a special program counter register (PC) that holds the address of the
current instruction being executed. As a MIPS programmer, you are not responsible for “fetching”
the next instruction from memory. This done automatically. Let’s have a look at how this is done.
Consider the simple case of a non-branching instruction such as add or lw or sw. The address of
the instruction that follows this non-branching instruction is, by default, the address of the current
instruction plus 4 (that is, plus 4 bytes or one word). Because we are assuming that each instruction
takes one clock cycle, at the end of clock cycle, PC is updated to PC+4.
The current instruction (add or lw or sw, ...) is fetched by using PC to select a word from the
text part of Memory, namely the word containing the current instruction. Later in the course, we
will see how this is done. For now, it is enough for you to understand that an address is sent to
Memory and the instruction at that address is read out of Memory. To summarize, the contents
of the PC (a 32 bit address) is sent to Memory and the instruction (also 32 bits) starting at that
address is read from Memory.
Memory
(instructions)
PC
4
32
various
parts of
instruction
(depends
on R, I, J
format)
32
last updated: 23rd Feb, 2016 1 lecture notes c
Michael Langer
COMP 273 13 - MIPS datapath and control 1 Feb. 22, 2016
Let’s next look at several examples of instructions and consider the “datapaths” and how these are
controlled.
Data path for add
What happens when the 32 bit add instruction is read out of memory? Recall that an add instruction
has R format:
field op rs rt rd shamt funct
numbits 6 5 5 5 5 6
The opcode field and funct fields together encode that the operation is addition (rather than some
other arithmetic or logical operation). The three register fields of the instruction specify which
registers hold the operands and which register should receive the output of the ALU. Thus, the op
code and funct fields are used to control what data gets puts on what lines and when data gets
written. I will say more about how the control signals are determined next lecture. For now, we
will concentrate on the datapaths, as shown in the figure below.
Memory
registers
12
5
(instructions)
PC
4
5
5
32
32
32
ALU op
control
opcode, funct
WriteEnable
("RegWrite")
Here is what happens during an add instruction:
new PC value is computed and written (at the end of clock cycle)
instruction is read (“fetched”) from Memory (details later in the course)
two ReadReg and the WriteReg are selected (recall lecture 6)
control signals for ALU operation are determined (to be discussed next lecture)
last updated: 23rd Feb, 2016 2 lecture notes c
Michael Langer
COMP 273 13 - MIPS datapath and control 1 Feb. 22, 2016
RegData values are read from two registers and input to ALU; ALU operation is performed
result is written into WriteReg (at the end of clock cycle)
The steps above can all be done in a single clock cycle, provided the clock interval is long enough
that all circuits have stabilized (and they would need to designed to ensure this). For example, the
ALU involves carry values which take time to ripple through.
Data path for load word (lw)
Recall that this instruction has I format:
field op rs rt immediate
numbits 6 5 5 16
An example is: lw $s0, 24($t3)
Here is the data path (including the PC update!)
Memory
registers
6
5
5
16
32
(instructions)
extend
sign
32
32
PC
4
32
ALUop
Memory
(data)
32
control
opcode
WriteEnable
("RegWrite")
For lw, the first three steps are the same as in the add instruction, but the remaining steps are
quite different.
new PC value is computed (it is written at next clock pulse)
instruction is read (“fetched”) from Memory
ReadReg and WriteReg selected and RegWrite is specified
base address of Memory word to be loaded is read from a register and fed to ALU
offset (16 bit immediate field) is sign-extended and fed to ALU
last updated: 23rd Feb, 2016 3 lecture notes c
Michael Langer