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Lecture 12

# COMP 273 Lecture Notes - Lecture 12: Nan, Exception Handling, Program Counter

Department
Computer Science (Sci)
Course Code
COMP 273
Professor
Piotr Przytycki
Lecture
12

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COMP 273 12 - MIPS co-processors Feb. 17, 2016
In today’s lecture we will look at two ”co-processors”, namely the ﬂoating point processor (called
CP1 or the FPU) and the kernel processor (called CP0 or the ’system control’ processor). We will
look at the MIPS assembly language instructions for this processor.
This is the last lecture above MIPS programming. After this, we will go back to the circuits
and connect the general ideas about circuits to the particular instructions we have seen in MIPS,
mostly CPU instructions but occasionally CP0 too.
Integer multiplication and division in MIPS
[ASIDE: The slides also start out with this mini-topic, but at the beginning of the lecture, I decided
to skip over this topic. I then returned to the topic (slides) a bit later.]
In Assignment 1, you built a simple but slow circuit for multiplying two unsigned integers and,
in lecture 7, I discussed more complicated circuits for how you could perform fast multiplication.
You should appreciate that there are many ways this could be done. Those details should now be
put ”under the hood”. Let’s just look at multiplication from the MIPS programmer’s perspective.
In MIPS assembly language, there is a multiplication instruction for signed integers, mult, and
for unsigned integers multu. Since multiplication takes two 32 bit numbers and returns a 64 bit
number, special treatment must be given to the result. The 64 bit product is located in a “product”
register. You access the contents of this register using two separate instructions.
mult \$s0, \$s1 # Multiply the numbers stored in these registers.
# This yields a 64 bit number, which is stored in two
# 32 bits parts: "hi" and "lo"
mfhi \$t0 # loads the upper 32 bits from the product register
mflo \$t1 # loads the lower 32 bits from the product register
You can only read from the product register. You cannot manipulate it directly. In MARS, the
product register is shown as two 32 bit registers, HI and LO. If the HI register has all 0’s, then the
product that is computed can be represented by 32 bits (what’s in the LO register). Otherwise, we
have a number that is bigger than the maximum int and it would need to be treated separately.
Details are omitted here.
What about division? To understand division, we need to recall some terminology. If we divide
one positive integer by another, say 78/21, or more generally ”dividend/divisor” then we get a
quotient and a remainder, i.e.
dividend = quotient divisor + remainder
e.g. 78 = 3 21 + 15
In MIPS, the divide instruction also uses the HI and LO registers, as follows:
div \$s0, \$s1 # Hi contains the remainder, Lo contains quotient
mfhi \$t0 # remainder moved into \$t0
mflo \$t1 # quotient moved into \$t1
The mult, div, mfhi, mflo are all R format instructions.
last updated: 18th Feb, 2016 1 lecture notes c
Michael Langer

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COMP 273 12 - MIPS co-processors Feb. 17, 2016
ﬂoating point in MIPS
As I also mentioned in lecture 7, special circuits and registers are needed for ﬂoating point op-
erations. The simple version of MIPS that we are using (called the R2000) was created back in
the mid-1980s. At that time, it was not possible to ﬁt the ﬂoating point circuits and registers on
the same physical chip 1as the chip that contained the CPU (including registers \$0-\$31, ALU,
integer multiplication and division). Instead, the ﬂoating point operations were carried out on a
physically separate chip called the ﬂoating point coprocessor or ﬂoating point unit (FPU) which in
MIPS is called coprocessor 1. The FPU for MIPS has a special set of 32 registers for ﬂoating point
operations, named \$f0, \$f1, ... \$f31.
Recall that double precision ﬂoats require two words. In MIPS, double precision numbers require
two registers. These are always consecutive registers, beginning with an even number register (\$f0,
\$f2, etc). Thus, there is no need to reference both registers in the instruction. For example, a
double precision number referenced by \$f2 in fact uses \$f2 and \$f3.
register
\$0,..,\$31
integer
arithmetic \$f0,.. \$f31
register floating point
multiplication
division
CPU (central processing unit)
logical ops multiplication
divison
arithmetic
int−float convert
mtc1
mfc1
Memory
(2^32 bytes)
sw
lw swc1
lwc1
"coprocessor 1"
FPU (floating point unit)
The MIPS instructions for adding and subtracting ﬂoating point numbers are of the form:
sub.s \$f0, \$f0, \$f2 # single precision sub
sub.d \$f2, \$f4, \$f6 # double precision sub
Having a separate FPU takes some getting used to. For example, the following instructions have
incorrect syntax and are not allowed.