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CMPT 150 (6)
Lecture

# Week9.pdf

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School
Department
Computing Science
Course
CMPT 150
Professor
Anthony Dixon
Semester
Fall

Description
A.H.Dixon CMPT 150: Week 9 (Oct 28 - 30) 63 31 MSI SEQUENTIAL SYSTEMS Just as sets of gates are often packaged in more complex entities because of their general utility, so it is the case with more complex sequential systems. The primary used of such systems is to provide memory for the istorage and manipiutlation of binary sequences. They can be classi▯ed by the way the storage is organized: Flip- ops (latches) : For the smallest memory requirements such as the storage of indi- vidual bits (eg ags), Registers : are sets of ip- ops or latches used to store binary sequences. Registers provide one or more of the following functions: ▯ Storage: The ability to be loaded with a binary sequence, ▯ Shifting: The ability to shift the binary sequence to the left or right with the sequence of ip- ops that de▯ne the register, ▯ Counting: The ability to increment or decrement the value stored in the regis- ter. Random Access Memories (RAM’s) : are sets of registers for storing a collection of binary sequences. RAM’s can be viewed as the hardware equivalent of 1-dimensional arrays. Viewed in this way, an address is equivalent to a subscript that determines which location in the RAM (i.e. 1-d array) a value is stored. 31.1 Parallel Load Registers Parallel load registers can store binary sequences in one step. In order to do so, all the bits of the binary sequence must be provided at the same time; that is, during the same clock period. The behavioral description of an n-bit parallel load register can be expressed as follows: Entity De▯ntion: d0 Q0 d1 Q1 . . . . dn−1 Qn−1 ld R Functional Speci▯cation: ld Function + + 0 Qn ▯ 1 ::: Q1 Q0+ = Qn-1 ::: Q1 Q0 1 Qn ▯ 1 ::: Q1 + Q0+ = dn-1 ::: d1 d0 A.H.Dixon CMPT 150: Week 9 (Oct 28 - 30) 64 EXAMPLE: The following example illustrates the design of a 4-bit storage register con- structed using D ip- ops. The behavioreal description is: d0 Q0 d1 Q1 d2 Q2 d3 Q3 ld R ld Function + + + 0 Q3 Q2 Q1 Q0+ = Q3 Q2 Q1 Q0 1 Q3 + Q2+ Q1 + Q0+ = d3 d2 d1 d0 To design this circuit from a function table would require a table with 2 = 512 rows. One strategy, called \bit-slice design", is to design a simpler storage register and then use it as a component to construct the larger register. In this case we design a 1-bit storage register ▯rst. Its functional speci▯cation can be expressed in an 8 row characteristic table: Q ld d Q+ 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 1 Constructing the ip- op input function table using the excitation table of the D ip- op: Q ld d Q+ D 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 Now D is a function of Q, ld and d, we can use a 3-variable K-map to obtain a minimal sum of products representation for D: D = Q▯ld + ld▯d Returning to the original problem, the design of a 4-bit register, we ▯rst observe that the 1-bit solution can be used to implement each bit of the 4-bit storage register. So we can construct a 4-bit storage register using 4 copies of the 1-bit storage register: A.H.Dixon CMPT 150: Week 9 (Oct 28 - 30) 65 ld 1−BIT STORAGE REGISTER D Q d d3 d2 d1 d0 ld d ld d ld d ld d ld 4−BIT STORAGE REGISTER 3 2 1 0 Q Q Q Q Q3 Q2 Q1 Q0 31.2 Shift Registers \Shift registers" are registers that can shift their contents 1-bit within the register. That is, they can shift the contents towards the most signi▯cant bit, called a \left shift", or towards the least signi▯cant bit, called a \right shift". The entity of a simple shift register with serial input x is given by: s x z0 z1 z2 z3 When the control input \s" is enabled, the contents of the register are moved one bit position towards either the most signi▯cant bit position or towards the least signi▯cant bit position. In a \left shift", the most signi▯cant bit is replaced by the bit to its right, and is lost. The least signi▯cant bit most into the next position to its left, leaving a \hole" in the least signi▯cant bit position. With a \right shift", the bits move one position to the right, leaving a \hole" in the most signi▯cant bit position. The \hole" is ▯lled by the value on the serial input \x". What value is placed in the \hole" in either a right shift or a left shift determines di▯erent types of shifts as follows: ▯ Shift Left Logical (sll): The least signi▯cant bit is ▯lled with the value ‘0’. ▯ Shift Right Logical (srl): The most signi▯cant bit is ▯lled with the value ‘0’. A.H.Dixon CMPT 150: Week 9 (Oct 28 - 30) 66 ▯ Shift Right Arithmetic (sra): The most signi▯cant bit is retained. That is, the value that was previously in the most signi▯cant bit position is retained in that position. ▯ Shift Left Circular (src): The most signi▯cant bit is copied to the least signi▯cant bit position. ▯ Shift Right Circular (slc): The least signi▯cant bit is copied to the most signi▯cant bit position. Shift registers are often called \serial load registers" because, unlike the parallel load reg- ister, the bits to be stored in a serial load register are input one at a time; that is, 1 bit per clock period. The basic shift register can be implmented using the same 1-bit storage register than was developed in order to implement an n-bit storage register. In this case, the output from one 1-bit storage register is passed to the next 1-bit storage register: x ld clk d ld d ld d ld d ld 3 2 1 0 Q Q3 Q2 Q1 Q0 31.3 Counters A common type of sequential digital circuit that occurs in many applications is called a \counter." Counters are circuits that repeatedl
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