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Lecture 10

COIS 2300H Lecture 10: WEEK 10 session 2 LEC NOTES
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Department
Computing & Information Systems
Course Code
COIS 2300H
Professor
Brian Srivastava

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WEEK 10 part 2
COIS 2300
Wednesday, March 14, 2018
Detechting the need to forward
Pass register numbers along pipline
ALU operand register numbers in EX stage are given by
ID/EX.RegistersRs
But only if forwarding instruction will write to a register
Double Data Hazard
Consider the sequence
add $1, $1, $2
add $1, $1, $3
add $1, $1, $4
Both hazards occur
Want to use the most recent
Revise MEM condition
How to Stall the pipline
Force control values in ID/EX register to 0
EX, MEM, and WB do nop (no-operation)
Stalls and Performance
Stalls reduce performance
But are required to get correct results
Reducing Branch Delay
Move hardware to determine outcome to ID stage
Target address adder
Register comparator
Dynamic Branch Prediction
In deeper and superscalar piplines, brnahc penalty is more significant
Use dynamic prediction
Branch prediction buffer (aka branch history table)
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Description
WEEK 10 part 2 COIS 2300 Wednesday, March 14, 2018 Detechting the need to forward Pass register numbers along pipline ALU operand register numbers in EX stage are given by IDEX.RegistersRs But only if forwarding instruction will write to a register Double Data Hazard Consider the sequence add 1, 1, 2 add 1, 1, 3 add 1, 1, 4 Both hazards occur Want to use the most recent Revise MEM condition How to Stall the pipline Force control values in IDEX register to 0 EX, MEM, and WB do nop (nooperation) Stalls and Performance Stalls reduce performance But are required to get correct results Reducing Branch Delay Move hardware to determine outcome to ID stage Target address adder Register comparator Dynamic Branch Prediction In deeper and superscalar piplines, brnahc penalty is more significant Use dynamic prediction Branch prediction buffer (aka branch history table)
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