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Lecture 10

COIS 2300H Lecture Notes - Lecture 10: Branch Predictor, Superscalar Processor, OperandPremium

2 pages85 viewsWinter 2018

Computing & Information Systems
Course Code
COIS 2300H
Brian Srivastava

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WEEK 10 part 2
COIS 2300
Wednesday, March 14, 2018
Detechting the need to forward
Pass register numbers along pipline
ALU operand register numbers in EX stage are given by
But only if forwarding instruction will write to a register
Double Data Hazard
Consider the sequence
add $1, $1, $2
add $1, $1, $3
add $1, $1, $4
Both hazards occur
Want to use the most recent
Revise MEM condition
How to Stall the pipline
Force control values in ID/EX register to 0
EX, MEM, and WB do nop (no-operation)
Stalls and Performance
Stalls reduce performance
But are required to get correct results
Reducing Branch Delay
Move hardware to determine outcome to ID stage
Target address adder
Register comparator
Dynamic Branch Prediction
In deeper and superscalar piplines, brnahc penalty is more significant
Use dynamic prediction
Branch prediction buffer (aka branch history table)
find more resources at
find more resources at
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