ENGG 2410 Lecture : Eng241-assign5-Sol-F12.pdf
11 Jan 2014
School
Department
Course
Professor
Document Summary
School of engineering, university of guelph, fall 2012. October 26, 2012: implement a binary adder with a dual 4-to-1 line mux: The top figure shows the connections required to implement f using the decoder. F (c) since the multiplexor to be used is 8-to-1 mux then we have to connect a (msb) to highest select line s2 b to s1 and c to s0. D will be used as an input to the 8-to-1 mux as seen in the. If a carry is produced discard the end carry. If the sum does not produce an end carry perform a correction, taking the 2"s complement of the sum and placing a minus sign in front. (a) 2"s complement of 10000 is 10000, therefore, 2 (b) 2"s complement of 01011 is 10101, therefore, 01011 (c) pad 100 with 3 zeros (000100), then the 2"s complement of 101000 is 011000. +011000 ( )011100 (d) 2"s complement of 1011100 is 0100100, therefore,
