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ENGG 2410 (12)
Lecture

# Eng241-assign5-Sol-F12.pdf

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School
University of Guelph
Department
Engineering
Course
ENGG 2410
Professor
Shawki M Areibi
Semester
Fall

Description
ENG2410 Assignment #5 Solutions School of Engineering, University of Guelph, Fall 2012 Prepared by: Shawki Areibi October 26, 2012 1. Implement a binary adder with a dual 4-to-1 line mux: 4 X 2 MUX X Y Cin S C Y S0 0 0 0 0 0 X S1 0 0 1 1 0 Cin D0(0) D0(1) 0 1 0 1 0 D0(2) Y0 S 0 1 1 0 1 D0(3) D1(0) Y1 C 1 0 0 1 0 D1(1) 1 0 1 0 1 D1(2) D1(3) 1 1 0 0 1 5V 1 1 1 1 1 2. Circuit Implementation using Decoders and Multiplexors: P (a) First we have to ﬁnd the sum of minterms of F. Accordingly, F(A,B,C,D) = m(2,3,5,6,8,9,12,14) (b) The size of the decoder is 4-to-16 line decoder. The top Figure shows the connections required to implement F using the decoder. 0 A 23 2 22 C 1 3 B 2 5 D 20 4−to−16 6 Decoder 7 F 9 10 11 12 14 15 (c) Since the Multiplexor to be used is 8-to-1 Mux then we have to connect A (MSB) to highest select line S2B to S a1d C to S . D0will be used as an input to the 8-to-1 Mux as seen in the Figure below. 1 A B C D F1 0 0 0 0 0 0 1 0 F1 = 0 0 0 1 0 1 C S 0 0 1 1 1 F1 = 1 S0 0 1 0 0 0 B S1
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