CEG 2136 Lecture Notes - Lecture 3: Arithmetic Logic Unit, Datapath, Circuit Diagram
11 May 2018
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CEG 2136 Lab 3 Page of 17
School of Electrical Engineering and Computer Science (EECS) Fall 2015
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LAB 3 Arithmetic Logic Unit
1. Purpose:
In this lab students will design, simulate, build and test an Arithmetic Logic Unit (ALU),
employing Quartus II as a development environment and the Altera DE2-115 board as
experimental platform. ALU has to execute 16 different operations on two operands of 4
bits, and will provide a 4-bit result along with 4 status bits (Overflow, Sign, Zero, Carry).
The input operands will be generated by slide switches, while the result and the status bits
will be displayed on LEDs.
2. Requirements of the Lab:
The following will be submitted in your report.
* Functional and truth tables, equations and schematics of your design
* Log of what you did
* Screen shots of all schematics and waveform diagrams
* Compilation, simulation and downloading messages (if any)
* Test results
3. Equipment and Supplies:
* Quartus II (student edition or web edition)
* Altera DE2-115 board with
- USB-Blaster cable - Power supply 12 VDC, 2A
4. References:
4.1. Chapter1 - 4 of the Text book: Computer System Architecture, Morris
Mano, 3rd Ed.
4.2. Course notesDE2-115 User Manual posted in the Documentation section
under the Laboratories tab of CEG2136 Virtual Campus.
5. PreLab – Design of the ALU
5.1. ALU structure
The Central Processing Unit (CPU) consists of a Control Unit (CU) and a Datapath
(execution unit – EU) shown in the block diagram of Figure 1. The CPU’s datapath
contains registers to store data (A, B, C) and control (S) / status (V,Z,N,Cy) information,
along an Arithmetic and Logic Unit (ALU). You have to design CPU’s datapath that can
perform arithmetic, shift and logic operations. Your datapath module will handle two
types of signals:
Data (inputs: A3-A0 and B3-B0, and outputs C3-C0) – marked in yellow
Control/status: S3-S0/(V, Z, N, Cy) – marked in light blue in Fig. 1
CEG 2136 Lab 3 Page of 17
School of Electrical Engineering and Computer Science (EECS) Fall 2015
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Figure 1: ALU block diagram
Figure 2 presents the ALU datapath. For testing purposes, since CU (the light-blue block
in Figure 2) is not designed and built in this lab, CU is replaced and emulated by 4 DIP
switches for generating the ALU control inputs (S3 - S0) and 4 LEDs to display the
ALU’s state indicators (V,Z,S,O). Operands A and B are generated manually by 8 DIP
switches, while the result C is displayed by other 4 LEDs.
Figure 2: ALU datapath
ALU is a combinational circuit which can execute any of the 16 micro-operations of
Table 1. The operation to be performed is set by the control word S3-S0 as follows:
the control signal S3 selects either the Arithmetic Circuit (AC) or the Logic and
Shifting Circuit (LSC) to perform the operation and send the result to the output C;
the control signals S2, S1, and S0 define the operations to be performed by each
circuit (AC or LSC).
Both inputs and outputs are stored in buffer registers (D flip-flops synchronized with the
same clock), A, B, and C, as shown in Figure 2. To operate at the highest speed, the ALU
datapath should be provided with both operands (A and B) and control bits (S3-S0) at
every consecutive clock. To insure a correct operation of the datapath, the total delay
Data Path
(EU)
S
A
V,
Z,
N,
Cy
B
C
CU
A3-A0
Data in
B3-B0
C3-C0
Data ou
t
Control Status
ALU
Data
Input
DATA PATH (EU)
ALU
CU
Outputs
=
ALU
Control
CU
Inputs
=
ALU
Status
CU
CEG 2136 Lab 3 Page of 17
School of Electrical Engineering and Computer Science (EECS) Fall 2015
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introduced by the ALU’s circuits should be smaller than the clock’s period and, as such,
the datapath can execute a micro-operation at every clock. The results (C3-C0) and V, Z,
S, Cy are provided on the next pulse following the change of A, B and S.
Table 1: arithmetic and logic micro-operations
Control Word ALU Data Micro-operation
Circuit S3 S2 S1 S0 Output Description
Arithmetic circuit
(AC)
0 0 0 0 BAC
Addition
0 0 0 1 1
BAC Add with carry
0 0 1 0
A
C
Transfer A
0 0 1 1 1
AC Increment A
0 1 0 0 BAC
Subtraction A - B with borrow (using 1’s
complement of B gives a result lower by 1
than a conventional subtraction).
0 1 0 1 1 BAC Subtraction A - B (use 2’s complement of B)
0 1 1 0 AC NOT A (complement A)
0 1 1 1 1 AC 2’s complement of A
Logic and shift
circuit (LSC)
1 0 0 0 "0000"
C Reset C
1 0 0 1 "1111"
C Set C
1 0 1 0 BAC
A AND B
1 0 1 1 BAC
A OR B
1 1 0 0 BAC
A EXCLUSIVE-OR B
1 1 0 1 BAC Reset A bits selected by “mask” B
1 1 1 0 AaC shl
Shift A left (signed multiplication by 2)
1 1 1 1 AaC shr
Shift A right (signed division by 2)
5.2. Hierarchical design
Since both the input and the output signals of ALU have 4 bits, the most effective way to
implement ALU is to devise it in a hierarchical manner. Files on the lowest level are 1-bit
full adder and 1-bit logic and shift circuit (LSC). The intermediate files will consist of a
4-bit register, a 4-bit arithmetic circuit (AC), a 4-bit logic and shift circuit (LSC), and a
state circuit. Finally, the file at the highest level will cover the complete circuit, loadable
to the UP2 board. The relation between these files is shown in figure 3. The parts in
yellow will be explained further in this document. For the preparation of this lab, you are
required to design and test the circuits coloured in green, i.e., the 1-bit LSC, the 4-bit
LSC, the 4-bit AC, and the state circuit.
Figure 3: Hierarchy of the files
Lab3top.bd
f
registe
r
4bit.bd
f
logiccircui
t
4bit.bd
f
arithcircuit4bits.bd
f
state4bits .bd
f
logiccircui
t
1bit.bd
f
fulladder1bit.bd
f
Document Summary
In this lab students will design, simulate, build and test an arithmetic logic unit (alu), employing quartus ii as a development environment and the altera de2-115 board as experimental platform. Alu has to execute 16 different operations on two operands of 4 bits, and will provide a 4-bit result along with 4 status bits (overflow, sign, zero, carry). The input operands will be generated by slide switches, while the result and the status bits will be displayed on leds: requirements of the lab: The following will be submitted in your report. * functional and truth tables, equations and schematics of your design. * screen shots of all schematics and waveform diagrams. * compilation, simulation and downloading messages (if any) * quartus ii (student edition or web edition) Usb-blaster cable - power supply 12 vdc, 2a: references: Chapter1 - 4 of the text book: computer system architecture, morris.
