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CSC258H1 (46)
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Department
Computer Science
Course
CSC258H1
Professor
Steve Engels
Semester
Winter

Description
LOGIC DEVICES o Half Adders  Building up from gates  A 2-input, 1-bit width binary adder that performs the following computations: o Some common and more complex structures  Multiplexers (MUX)  Adders (half and full)  Subtractors  Comparators  Decoders  A half adder adds two bits to produce a two-bit sum  Seven-segment decoders  The sum is expressed as a sum bit S and a carry bit C o Certain structures are common to many circuits, and have block  Half Adder Implementation elements of their own  Equations and circuits for half adder units are easy to  Karnaught map review – moved to jan18ce define (even w/o k-maps)  Multiplexers (MUX) o Behavior:  output is X if S = 0; otherwise output is Y if S = 1 o Full Adders  Similar to half-adders, but with another input Z, which represents a carry-in bit o Multiplexer design X Y S M M  C and Z are sometimes labels asoutand Cin  When Z is 0, the unit behaves exactly like a half adder 0 0 0 0 0 0 1 0  When Z is 1, the full adder performs the following computations 0 0 1 0 1 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1  Full Adder Design X Y S C S C 0 0 0 0 0 0 0 1 0 0 0 1 0
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