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CSC258H1 (46)


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Computer Science
Steve Engels

 Reading from latches o This is the typical symbol for a clock SR Latch o Need some sort of timing single  to signal the circuit when the output may be sampled  to differentiate btwn single high value and two high values in a row o Clock Signals – regular pulse signal, where the high value indicates that the output of the latch may be sampled o This only allows the S and R signals to affect the circuit when the  Usually drawn as: clock input (C) is high o Note: the small NOT circle afteroutput is simply the notation to use to denote the inverted output value, it’s not an extra NOT gate o Assuming the clock is 1, still have a problem when S = 1 and R =1  Signal restrictions o What’s the limit to how fast the latch circuit can be sampled? since the state of Q is indeterminate o Determined by  Better design: prevent S and R from both going high  Latency time of transistors  D latch o By making the inputs to R and S dependent on a single signal D, you  Setup and hold time  Setup time for clock signal avoid the indeterminate state problem  Jitter o The value of D now sets output Q low or high  Gibbs phenomenon o Frequency = how many pulses occur per second, in Hertz (Hz)  Clocked SR latch o By adding another layer of NAND gates to the SR latch, results in a clocked ̅̅ latch circuit o This clock (C) is often connected to a pulse singal that alternates o Truth table assuming C is high regularly between 0 and 1 C o Behavior same as SR latch but w/ timing:  Star off with S = 0 and R = 1 1 0 0 0 1 0 1 1  If C = 1, the first NAND gates invert those values, which get 1 1 0 0 inverted again in the output 1 1 1 1  Setting S = 0 and R = 0, maintains the output value o Good design, but still has problems, i.e. timing issues  Consider the circuit on the right  When the clock signal is high, the output looks like the waveform below:  Output keeps toggling back and forth  Preferable behavior  Have output change only once when the clock pulse
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