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CSC258H1 (46)


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Computer Science
Steve Engels

o Timing waveforms  Week 8 Review  Reading and writing of signals to and from memory is expensive o Q1: a RAM unit has 6 address bits going into it; given a 32-bit  Several clock cycles to access memory vs. 1 clock cycle for architecture, how many 6ytes is the RAM unit able to store? accessing registers  6 address bits  2 lines of memory  Different architecture will have different delays  Total: 64 lines of memory (memory slots)  In this example there is a 75ns write cycle between the start of  32-bit architecture  4 bytes per memory address the write process and the point at which the write process is  RAM capacity = 64*6 = 256 bytes of memory complete o Q2:  Interval 1 = Setup Address Time  for the address to be written at to be available for writing  Interval 2 = Setup Data Time  for the data values to written at the address  Interval 3 = Hold Data Time  To signal done writing, make sure address stop writing well before data becomes invalid/unavailable  Timing constraints for reading from memory  Address Acces Time (t ) – time needed for address AA values to be stable before reading data values (~10ns)  Output Hold Address (t OHA) – time to hold data high after address values change b/c of time takes to send received ack msg to address means data will hold out a bit longer after address is invalid  Read easy b/c basically is listening, doesn’t need to o Q3 change Read/Write signal
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