# CSC258H1 Lecture Notes - Clock Signal, Gibbs Phenomenon, Truth Table

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Published on 20 Apr 2013
School
UTSG
Department
Computer Science
Course
CSC258H1
Professor
o Need some sort of timing single
to signal the circuit when the output may be sampled
to differentiate btwn single high value and two high values in a
row
o Clock Signals regular pulse signal, where the high value indicates
that the output of the latch may be sampled
Usually drawn as:
Signal restrictions
o What’s the limit to how fast the latch circuit can be sampled?
o Determined by
Latency time of transistors
Setup and hold time
Setup time for clock signal
Jitter
Gibbs phenomenon
o Frequency = how many pulses occur per second, in Hertz (Hz)
Clocked SR latch
o By adding another layer of NAND gates to the SR latch, results in a
clocked
latch circuit
o This clock (C) is often connected to a pulse singal that alternates
regularly between 0 and 1
o Behavior same as SR latch but w/ timing:
Star off with S = 0 and R = 1
If C = 1, the first NAND gates invert those values, which get
inverted again in the output
Setting S = 0 and R = 0, maintains the output value
Now set C = 1
Even if the inputs change, the low clock input prevents
the change from reaching the second stage of NAND
gates
Result: the clock needs to be high in order for the inputs to have
any effect
o Truth table assuming C is high
C

Result
1
0
0
0
0
No change
1
0
0
1
0
Reset
1
0
1
0
1
Set
1
0
1
1
?
???
1
1
0
0
1
No change
1
1
0
1
1
Reset
1
1
1
0
0
Set
1
1
1
1
?
???
o This is the typical symbol for a clock SR Latch
o This only allows the S and R signals to affect the circuit when the
clock input (C) is high
o Note: the small NOT circle after
output is simply the notation to
use to denote the inverted output value, it’s not an extra NOT gate
o Assuming the clock is 1, still have a problem when S = 1 and R =1
since the state of Q is indeterminate
Better design: prevent S and R from both going high
D latch
o By making the inputs to R and S dependent on a single signal D, you
avoid the indeterminate state problem
o The value of D now sets output Q low or high
o Truth table assuming C is high
C

1
0
0
0
1
0
1
1
1
1
0
0
1
1
1
1
o Good design, but still has problems, i.e. timing issues
Consider the circuit on the right
When the clock signal is high, the output looks like the
waveform below:
Output keeps toggling back and forth
Preferable behavior
Have output change only once when the clock pulse
changes
SR master-slave flip-flop
o Solution: create disconnect between circuit output and circuit input,
to prevent unwanted feedback and changes to output
o A flip-flop is a latched circuit whose ouput is triggered with the rising
edge or falling edge of a clock pulse
Ex. the SR master-slave flip-flop
o SR flip-flops still have issues of unstable behavior
o SR flip-flops still have issues of unstable behavior
Solution: D flip-flop
o Connect D latch to the input of a SR latch
o Negative-edge triggered flip-flop (like the SR)
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## Document Summary

Reading from latches: need some sort of timing single. To signal the circuit when the output may be sampled. To differentiate btwn single high value and two high values in a row: clock signals regular pulse signal, where the high value indicates that the output of the latch may be sampled. Signal restrictions: what"s the limit to how fast the latch circuit can be sampled, determined by. Gibbs phenomenon: frequency = how many pulses occur per second, in hertz (hz) Star off with s = 0 and r = 1. If c = 1, the first nand gates invert those values, which get inverted again in the output. Setting s = 0 and r = 0, maintains the output value. Even if the inputs change, the low clock input prevents the change from reaching the second stage of nand gates.