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Published on 20 Apr 2013
School
UTSG
Department
Computer Science
Course
CSC258H1
Professor
o Timing waveforms
Reading and writing of signals to and from memory is expensive
Several clock cycles to access memory vs. 1 clock cycle for
accessing registers
Different architecture will have different delays
In this example there is a 75ns write cycle between the start of
the write process and the point at which the write process is
complete
Timing constraints for reading from memory
values to be stable before reading data values (~10ns)
Output Hold Address (tOHA) time to hold data high after
ack msg to address means data will hold out a bit longer
Read easy b/c basically is listening, doesn’t need to
Timing constraints for writing to memory
values to be stable before turning on the write signal
(10ns)
Address Width Time (tAW) time that write signal is high
(~8ns)
Setup Data Time (tSD) time for data values to be set up
at destination (~6ns)
Hold Data Time (tHD) time that data will remain held
high after write signal falls (~10ns), make sure address
stop writing well before data becomes invalid
o Memory vs. registers
Memory house most of the data values being used by a program
Registers are more local data stores, meant to be used to
execute instruction
Registers are nt menat to host memory between
instructions (like scrap paper for calculation)
Exception is the stack pointer register, which is
sometimes in the same register file as the others
Week 8 Review
o Q1: a RAM unit has 6 address bits going into it; given a 32-bit
architecture, how many bytes is the RAM unit able to store?
6 address bits 26 lines of memory
Total: 64 lines of memory (memory slots)
32-bit architecture 4 bytes per memory address
RAM capacity = 64*6 = 256 bytes of memory
o Q2:
Interval 1 = Setup Address Time
for the address to be written at to be available for writing
Interval 2 = Setup Data Time
for the data values to written at the address
Interval 3 = Hold Data Time
To signal done writing, make sure address stop writing
well before data becomes invalid/unavailable
o Q3
Identify the components in the diagram
1. Program Counter 5. ALU
2. Memory 6. Memory data register
3. Instruction Register 7. Signed extend
4. Register 8. Shift left 2
What does the program counter do?
PC tracks which instruction the processor is currently
executing or to be executed by the processor
How does the instruction register know what type of instruction
it needs to perform?
From the OP code: the first 6 bits of the instruction,
determines the type I, J or R type
o Q4 same as week 9 review Q1
o Q5 same as week 9 review Q2
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## Document Summary

Reading and writing of signals to and from memory is expensive. In this example there is a 75ns write cycle between the start of the write process and the point at which the write process is complete. 6 address bits 26 lines of memory. Total: 64 lines of memory (memory slots) 32-bit architecture 4 bytes per memory address. Ram capacity = 64*6 = 256 bytes of memory: q2: Interval 1 = setup address time for the address to be written at to be available for writing. Interval 2 = setup data time for the data values to written at the address. To signal done writing, make sure address stop writing well before data becomes invalid/unavailable. Address acces time (taa) time needed for address values to be stable before reading data values (~10ns)