CSC258H1 Lecture Notes - Address Decoder, Food Processor, Readwrite

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Published on 20 Apr 2013
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Registers and Memory the “Storage Thing”
o Beyond the units that store a single value (program counters,
instruction registers) there are units in the CPU that stores multiple
data values for use by the CPU:
REGISTERS small number of fast memory units that allow
multiple values to be read and written simultaneously
Ex. in A*B multiplication, any intermediary values is
stored here, such as P at each iteration
32 spots, most are allocated for special purpose access
only to 20 25 of them
MAIN MEMORY larger grid of memory cells that are used to
store the main information to be processed by the CPU
RAM sticks, made up of registers
Ex. in A*B multiplication, final P value is stored inhere
o Anology: if ALU is a food processor
Register = fridge, Memory = supermarket, Hard drive = farm
Each stage access speed grows exponentially
b/c at each stage there are exponentially more possible
registers to read/write
o Each register have a wire to it to known when read/write a value
Only 1 register activated at a time
o Multiplexer before the output A and B controls which registers are
being read via the outputs
Registers are constantly outputting its value, the mux controls
which are being used by an ALU operation
o Eletronic Memory
Like register files, main memory is made up of a decoder and
rows of memory units
One-hot decorer The decoder takes in the m-bit binary address
and activates a single row in the memory array
an address accesses 1 of 2m possible n-bits lines
size of m is dependent on the size of the memory stick
32-bit or 64 bit is the common value for n
Ex. 3-bit address decoder that activates a 8-bit row in the
memory
o Controlling the flow
Memory has a conduct (bus) from the main part (registers, ALU)
to where memory is b/c memory is separated from the CPU
There is a main line from memory to CPU since only need
to access one line in memory at a time; not separate lines
for each lines of memory; other lines are sealed
Implication: CPU only need m-bits to connect to memory,
rather than accessing 2m connections to memory
Since some lines (bus) will now be used for both input and
output, use new gate called the tri-state buffer
A bus is n-bit wide, access entire row of memory at once
When WE (write enable) signal is low, buffer output is a high
impedance signal
output is either connected to high voltage or the ground
Use WE to access one line of memory at a time, while WE
is high for one line its low for all the other lines
Y is the n-bit bus shared between all the lines of memory
WE = 1 then output Y is input A
WE = 0 then doesn’t matter what A is Y is not connected
can’t access specific bit of 1 line of memory, must extra
entire Y (n-bit bus) and extract the relevant bits
o Storage cells
Each row of memory is made of n storage cell
Multiple ways of representing these cells
Select bit here is the same as WE
Ex. RAM cell vs. DRAM IC cell
o Ram slice model
Word select signals determine which row to send out on the
C lines
bit select signals determine which column is being read
WE
A
Y
0
X
Z
1
0
0
1
1
1
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Document Summary

Registers small number of fast memory units that allow multiple values to be read and written simultaneously. Ex. in a*b multiplication, any intermediary values is stored here, such as p at each iteration. Memory has a conduct (bus) from the main part (registers, alu) to where memory is b/c memory is separated from the cpu. There is a main line from memory to cpu since only need to access one line in memory at a time; not separate lines for each lines of memory; other lines are sealed. Implication: cpu only need m-bits to connect to memory, rather than accessing 2m connections to memory. 32 spots, most are allocated for special purpose access. Since some lines (bus) will now be used for both input and output, use new gate called the tri-state buffer. A bus is n-bit wide, access entire row of memory at once. When we (write enable) signal is low, buffer output is a high impedance signal.

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