mipssheets.pdf

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Department
Electrical Engineering and Computer Science
Course
EECS 2021
Professor
All Professors
Semester
Winter

Description
MIPS CPU INSTRUCTIONS for COSC2021 REGISTERS Arithmetic Family (14) TYPE 0x ORDER 0 0 1 at add(u) reg0, reg1, reg2 R 20 (21) 1,2,0 2 v0 addi(u) reg0, reg1, imm I 08 (09) 1,0 sub(u) reg0, reg1, reg2 R 22 (23) 1,2,0 3 v1 4 a0 mult(u) reg1, reg2 R 18 (19) 1,2 5 a1 div(u) reg1, reg2 R 1A (1B) 1,2 6 a2 slt(u) reg0, reg1, reg2 R 2A (2B) 1,2,0 7 a3 slti(u) reg0, reg1, imm I 0A (0B) 1,0 8 t0 Logical Family (13) 9 t1 10 t2 and reg0, reg1, reg2 R 24 1,2,0 11 t3 andi reg0, reg1, imm I 0C 1,0 12 t4 or reg0, reg1, reg2 R 25 1,2,0 13 t5 ori reg0, reg1, imm I 0D 1,0 14 t6 15 t7 xor reg0, reg1, reg2 R 26 1,2,0 16 s0 xori reg0, reg1, Imm I 0E 1,0 nor reg0, reg1, reg2 R 27 1,2,0 17 s1 18 s2 sllv reg0, reg1, reg2 R 04 2,1,0 19 s3 sll reg0, reg1, imm R 00 zero,1,0 20 s4 srlv reg0, reg1, reg2 R 06 2,1,0 21 s5 srl reg0, reg1, imm R 02 zero,1,0 22 s6 srav reg0, reg1, reg2 R 07 2,1,0 23 s7 24 t8 sra reg0, reg1, imm R 03 zero,1,0 25 t9 Jump Family (3) 26 k0 j 02 imm J 27 k1 reg,0… jr 08 reg R 28 gp jal 03 imm J 29 sp 30 fp Branch Family (6) bgtz reg, imm I 07 reg,zero 31 ra bgez reg, imm I 01 reg,one SYSCALL bltz reg, imm I 01 reg,zero blez reg, imm I 06 reg,zero Service Seetdurn beq reg1, reg2, imm I 04 1,2 Print int 1 a0 bne reg1, reg2, imm I 05 1,2 Print float 2 f12 Print double 3 f12 Load / Store Family (8) lw reg0, imm (reg1) I 23 1,0 Print string 4 a0 lh(u) reg0, imm (reg1) I 21 (25) 1,0 Read int 5 v0 Read float 6 f0 lb(u) reg0, imm (reg1) I 20 (24) 1,0 sw reg0, imm (reg1) I 2B 1,0 Read double 7 f0 Read string 8 a0/1 sh reg0, imm (reg1) I 29 1,0 Allocate 00 sb reg0, imm (reg1) I 28 1,0 Print char 11 a0 "Other" Family (6) lui reg, imm I 0F zero,reg ASCII CODE syscall R 0C 0-9 start at 48 or 0x30 0,0,reg mflo12 reg R A-Z start at 65 or 0x41 reg,0,0 mtlo13 reg R a-z start at 97 or 0x61 0,0,reg 10 reg R mfhi ' ' space at 32 or 0x20 mthi reg,0,0reg R11 CSE2021 MIDTERM Page 12 of 12 1 ARITHMETIC CORE INSTRUCTION SET 2 OPCODE / FMT /FT FOR- / FUNCT M I P S Reference Data NAME, MNEMONIC MAT OPERATION (Hex) Branch On FPTrue bc1t FI 11/8/1/-- CORE INSTRUCTION SET OPCODE if(FPcond)PC=PC+4+BranchAddr (4) FOR- / FUNCT Branch On FP False bc1f FI if(!FPcond)PC=PC+4+BranchAddr(4) 11/8/0/-- NAME, MNEMONIC MAT OPERATION (in Verilog) (Hex) Divide div R Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt] 0/--/--/1a Divide Unsigned divu R Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt] (6) 0/--/--/1b Add add R R[rd] = R[rs] + R[rt] (1) 0 / 2hex Add Immediate addi I R[rt] = R[rs] + SignExtImm (1,2) 8 FP Add Single add.s FR F[fd ]= F[fs] + F[ft] 11/10/--/0 hex FP Add add.d FR {F[fd],F[fd+1]} = {F[fs],F[fs+1]} + 11/11/--/0 Add Imm. Unsigned addiu I R[rt] = R[rs] + SignExtImm (2) 9hex Double {F[ft],F[ft+1]} 0 / 21 FP Compare Single c.x.s* FR FPcond = (F[fs] op F[ft]) ? 1 : 0 11/10/--/y Add Unsigned addu R R[rd] = R[rs] + R[rt] hex And and R R[rd] = R[rs] & R[rt] 0 / 2hex FP Compare c.x.d* FR FPcond = ({F[fs],F[fs+1]} op 11/11/--/y Double {F[ft],F[ft+1]}) ? 1 : 0 And Immediate andi I R[rt] = R[rs] & ZeroExtImm (3) chex * (x isq ,lt, orle) (op is ==, >> shamt 0/--/--/3 Or or R R[rd] = R[rs] | R[rt] 0 / 2hex Store FP Single swc1 I M[R[rs]+SignExtImm] = F[rt] (2) 39/--/--/-- Or Immediate ori I R[rt] = R[rs] | ZeroExtImm (3) dhex Store FP sdc1 I M[R[rs]+SignExtImm] = F[rt]; (2) 3d/--/--/-- Set Less Than slt R R[rd] = (R[rs] < R[rt]) ? 1 : 0 0 / 2hex Double M[R[rs]+SignExtImm+4] = F[rt+1] Set Less Than Imm. slti I R[rt] = (R[rs] < SignExtImm)? 1 : 0 (2) ahex FLOATING-POINT INSTRUCTION FORMATS Set Less Than Imm. R[rt] = (R[rs] < SignExtImm) sltiu I bhex FR opcode fmt ft fs fd funct Unsigned ? 1 : 0 (2,6) 31 26 25 21 20 16 15 11 10 6 5 0 Set Less Than Unsig.sltu R R[rd] = (R[rs] < R[rt]) ? 1 : 0 (6) 0 / 2hex FI opcode fmt ft immediate Shift Left Logical sll R R[rd] = R[rt] << shamt 0 / 0hex 31 26 25 21 20 16 15 0 Shift Right Logical srl R R[rd] = R[rt] >> shamt 0 / 0hex PSEUDOINSTRUCTION SET 1. Pull aStore Byteration to sbparate IarM[R[rs]+SignExtImm](7:0) =ttom side (co28hex 3 and 4) together NAME MNEMONIC OPERATION R[rt](7:0) (2) Branch Less Than blt if(R[rs]R[rt]) PC = Label Store Conditional sc I 38hex Branch Less Than or Equal ble if(R[rs]<=R[rt]) PC = Label R[rt] = (atomic) ? 1 : 0(2,7) Branch Greater Than or Equal bge if(R[rs]>=R[rt]) PC = Label sh M[R[rs]+SignExtImm](15:0) = 29 Store Halfword I R[rt](15:0) (2)
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