EEE 425 Lecture Notes - Lecture 1: Vaud, Vehicle Identification Number, Pmos Logic
7 Jul 2016
School
Department
Course
Professor
Document Summary
Submission: prepare a concise report (< 5 pages) with important results only. You don"t have to include the entire set of your circuit schematics or layout plots. Place the report in assignment at myasu with the filename as: eee425_lab_1_your name. The objective of this software lab is to exercise spice circuit simulations with cadence tools. The technology used in this course is a 32nm technology. All the mosfets have the minimum gate length, i. e. , l=30nm. Get familiar with the tools and the simulation environment. No submission needed for this problem: technology characteristics. Figure 1 shows a single nmos and pmos. In this problem, we calibrate the iv characteristics of this. Ids: for the nmos, (1) plot out ids vs. vds in one figure, for. Vds=0-1. 05v, at the step size of 1mv; (2) plot out log(ids) vs. vgs, for vds=0. 15v and. 1. 05v; vgs=0-1. 05v, at the step size of 1mv: repeat step (1) for the pmos transistor.
