COMPSCI 61C Lecture Notes - Lecture 15: Arithmetic Logic Unit, Railways Act 1921, Square Wave
28 Aug 2017
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Mt1 covers up to and including 02/15 lecture (call 2) Synchronous digital systems consist of two basic types of circuits. Output is a function of inputs only, not a history of its execution. Ip- op name because output ips and ops between 0 and 1. D is data input, q is data output. Positive edge triggered (triggers when signal goes up) or negative. On the rising edge of the clock, the input d is sampled and transferred to the output. At all other times, the input d is ignored. Setup time: when input must be stable before edge of the click. Hold time: when input must be stable after edge of the click. Clk-to-q delay (time click to data): how long it takes output to change, measured from rising edge of clk. Clock signal(s) connect(s) only to clock input of registers. Clock (clk): steady square wave that synchronizes the system.
