CS 120 Lecture Notes - Lecture 12: Finite-State Machine, Overclocking

• School: Binghamton University
• Department: Computer Science
• Course: CS 120
• Professor: Steven Moore

Document Summary

D-latch: a write-enabler connected to an rs latch that tells the circuit whether the information can be changed. If the write-enabler is 1, the state can be changed. If it is 0, the circuit is read-only, and the state is accurate. Memory is stored in at least 1 byte (8 bits). No information stored is less than 1 byte. For 64 (cid:271)it (cid:373)a(cid:272)hi(cid:374)es, there"s a register with 64 rs latches connected to 1 write-enabler. Clock cycle: the time it takes to read and write on a computer. The term so-and-so ghz is the clock cycle. Trying to read and write faster than the clock cycle can fry the processor or lead to corrupted memory, be(cid:272)ause the (cid:373)e(cid:373)ory (cid:272)a(cid:374)"t get lat(cid:272)hed i(cid:374) fast e(cid:374)ough (cid:271)efore it swit(cid:272)hes (cid:271)a(cid:272)k to write or read again. Many computers actually have a clock cycle that is much longer than necessary, just to avoid overclocking in general.