CMPEN331-02-2014.pdf

2.1 Week [email protected] CMPEN 33Spring 2014 Penn State, University Park YuanComputer Science and Engineering Slides adapted and updated from those developed by Profs. Irwin, Patterson and Heller Computer Organization and Design PSU, CMPEN 331, Spring 2014 2.2 DevicesorkInput Output Memory 00000100000 contents Reg #2 00010 ADD directed by the Control 00010 00100 results put in Reg #2 The Datapath exeCo0ntr0Datapathts Reg #4 Processor Memory stores both instructions and data Review – The Execute Cycle PSU, CMPEN 331, Spring 2014 2.3 objbitodeences representing characters, numbers, etc.   Memory sto InstrontriluDutdinneonsaaru,ecemdifuerto Reviw – The Fe1. 2.xecu3. 4. 5. 6. PSU, CMPEN 331, Spring 2014 2.4 Decode Fetch Exec so that the instructions can e datapath’s functional units, adder) and ore data to memory needs to have circuitry to needs to have circuitry to DecideDwcsiinformation flows between datapath components l l l l Exestorage locations (e.g., register file) Control l l l Datapath Review – Processor Organization PSU, CMPEN 331, Spring 2014 2.5 data Memory C compilerroll (machi(machi)e code)urce code inrg Accounting prog Inarusuton,uamrsnebsrssoaesfdnbmlefroritentto)bers and,t l l 1. 2. Stored-program concept Two Key Principles of Machine Design PSU, CMPEN 331, Spring 2014 2.6 in text), produces object fileinstructions CompLnioadeadretostobjflitpt,ctobijrtbtimwemroryll treated as data AladaPte.rlis – “One man’s program is another man’s Data or Instructions ? PSU, CMPEN 331, Spring 2014 2.7 then your system is insecure, misinterpret the bits, so arbitrary dicate read, write and execute float vs. int Thdatncinwbltekhaasei.structions,fmee AtwnhanmtoistdntionsdresalybhdaAtmseeitfigittdctomdsa Desig Chalenge  PSU, CMPEN 331, Spring 2014 2.8 the and performance hardware cost consumption, maximize reliability (whose job it is to translate programs written in a high Wecolevand minimizingassembly code) while maximizing The language Oour target:theine IPS ISA: maximizewww.mips.com, minimize cost,ower Assemly Language nstructions PSU, CMPEN 331, Spring 2014 2.9 what should the instruction set opcoder–itmchymHhatinedisgnrmd/eolttesetebotiorta DifeurtwtcompanBeriahtvAsneicheeidn2orrceendhArtieax Ass embly Langu age Instructio ns PSU, CMPEN 331, Spring 2014 2.10 believed there are) many old MIPS, xPAist,PonyrPr,vRngwec.known example RISC C=ISeCduoidmInmtulnsto0andsusportlgroldansstu      RISC vs. CISC PSU, CMPEN 331, Spring 2014 2.11 fixoad-tictinseugtosrofadfrmSriilefitfedesimlrtm.s Some examplesN ofotutwsydtiaFesdrncISowscoetier(bnin RISC– Reduced Instrution SetComputer PSU, CMPEN 331, Spring 2014 2.12 ster file (load-store machine) fixdmsileinstleiefiesierftiiasetrcgidereidnrgoioertsieg Simplicity favmoaslergulaMraeke theGcoomdmdonigcaseefaasnds good compromises MIP S (RISC) Design Pr inciple s PSU, CMPEN 331, Spring 2014 2.13 commpareregieeoyfradsisplyteo ▶ ▶ ▶ fixdpczdeislrayiohs,smlwllnttutii.tronrugbiesffedares regsuariticiaeknarieslhigheeaiinformdpntrtimtlntaticocst sts Simplicity favo Srs arleurlsrfyster MIPS RISC) Design Prnciples PSU, CMPEN 331, Spring 2014 2.14 remain common in the future?hine)s) tosions that limit you discover which are thechoices. Evaluate , etc. their good points and bad, and ,ge blt , but not bne , arithmetic operands from egeie instruction formats, as similar as possible FinIycomymuooocasesat?IWtillarse cfallprograms, or only the ones Make the common cG aoeofadst sign demands good compromises MIPS (RISC) Design Principles   PSU, CMPEN 331, Spring 2014 2.15 operation register three one source1 op source2  ) addsub$t0$,t0,s1,s1,s2$s2 destination Operand order is fixed (the destination is specified first)  MIPS asseEmaElyoperandseiTitfileirptdforrcceonax MIP S Arithm  eic Instructi ns PSU, CMPEN 331, Spring 2014 2.17 , c is $s1 and the result is $s3 , whath = (b - c) + d;r equivalent to , and d is stored in $s0 $s2 Assumito the C statementtored in register  Compiling More Complex Statemen ts, CMPEN 331, Spring 2014 2.19 1 2 s 3va0absc$sdg$it$rtemp $t0 Regh=t(se–trtn:=dbgwsttddps,uamgite0,i,ns1,0,$s$2s3 How  to Co mpile Co de by Hand PSU, CMPEN 331, Spring 2014 2.20 ompared to some other ISAs) Make the common case fast & TwoOneawporsortSmallrs.,Aei)ceaCDg)t(EsF)caedo ● ● ● ● ● Thirty-two 32-regtseasaccersrtvmpieretdensory Op eurrbdsrofffpthmieliccattruacionntmiRedtiseeromaataim MIPS Register File PSU, CMPEN 331, Spring 2014    2.22 call? yes yesyesyes Mupreserveda o ) n ) no (n.a.) call or by callee hardware hardware Usage for assembler for opna(nga)ystem no (n.a.) an be overwritten by reserved reserved rs to the caller”; circumstances” 0 1 constant 0 ( 2-34-78-11623426-27avedmemrporsriesnteriteno no ( Registerr $at $gp$sp$fp$ra Name $zero Register $v0$-$t-$s0 - $s70 -t$k1 “no” = “caller-saved if it matte MIPS Register Conventions – name PU,nMENu3Sping 2014 2.24 DevicesoInput Output must be in registers Memory operands Control Processor Datapath But only thirty-two registers are prWhat about programs with lots of variables? Arithmetic instruction The compiler associates variables with registers   Registers vs. Memory PSU, CMPEN 331, Spring 2014 2.25 integr,roat,grucures,oessts, dynamic data RegisMtainmrepeofyrioatihomoiierm,eoatomnw,lokyivalu Mem  ory Op erands PSU, CMPEN 331, Spring 2014 2.26 of a word is at lowest byte ored at consecutive addresses The bytesofiesLndiiE:aeismseanfcaiftfcanabfoerbtyewesr Memory W orbdstareddlieseeddin memory, for efficiency Mem  ory A ddressing PSU, CMPEN 331, Spring 2014 2.27 Words Bytes30 data 32 2 The word ? locaions4GB(1 GW) address of the 8 4 0 = 4 Bytes = 1 Word Memory 1001 … 0…12 bits 32 32 acts as the index into the memory red/wrtldrtda/drte data 32 address the memory The data stored in Processor Mem Aomremisorylarge, single-dimensional array of bytes Processor – Memory Interconnectio PnUsMPEN 331, Spring 2014 2.28 Arrayruct.merraer[j] If nlobajcsioaarcm.byocordoceutrenehascoeytinhstoefo Byte Add ress es for Large O bjects ( ASCrEN3s,pg01 2.29 word in memoryparc, HP PAittle endian byte 0 MIPS bytes 1 2 3 - the memory address of a lsb = least significant bit/byte leftmost byte is word a0dress1 : rightmost byte is word address msb be on natural IBM 360Intel 80x86, DEC Vax, DEC Alpha (Windows NT) big endian byte 0 AlimumstIPS-32)ritabdtbytengainsviuseful, most architectures also     msb = most significant bit/byte, Word Addresses vs. Byte Addresse PU, CMPEN 331, Spring 2014 2.30 Pictures from Wikipedia PSU, CMPEN 331, Spring 2014 2.32 memory 10 insholds 24s for summing the constant $s3 (loade to (load) or read from (store) – 10 10 data tra28fer32 lw $t0,$t4(,$83)$s3#loa#dstorrd worodm memource) MIPaccessing memory (assume porriegnitfr–eonfetuctb Accessing Memory   PSU, CMPEN 331, Spring 2014 2.34 . . . 0001 24 20 16 12 8 4 0 summing the in memory location 16 32 bit Data Word Address . .0..10.01.00.01.10.00 0 0 Memory . . . 0001 holds 8 t0, 4($s3) #what? is loaded into $t0 Theconconae$s3ortftheosthconistruciitnr(theobffset) and the MI PS Memory Addressing lw sw $t0 PU, PN 3sSr)2014 2.36 and that the base $s2 , what are the three statements $s3 lw st0,sw$tt0,)$t0,$s$s2 A[8] = A[2] - b +12+8 +4 . . . $s3$s3$s3$s3 Asadin MIPS assembly code for the C statement . . . A[3]A[2]A[1]A[0] Compiling with Loads and Stores PSU, CMPEN 331, Spring 2014 2.38 , $s3 , and , and variables b, c, $s2 $s4 $s1 c = A[i] - b AsAsuannrespectveby,codmefetthheCMstaSement  +12+8 +4 . .$s4$s4$s4$s4 . . . A[3]A[2]A[1]A[0]daddad1$l$1sub$t0$s01$r#a Compiling with a Variable Array Ind PexCMPEN 331, Sprin