ECE 27000 Lecture Notes - Lecture 9: Clock Signal, Propagation Delay, Sequential Logic

• School: Purdue University
• Department: Electrical & Computer Engr
• Course: ECE 27000
• Professor: Meyer

Document Summary

We store a bit of information using a d latch. A d latch is an s r latch with d connected to the s input a(cid:374)d d" (cid:272)o(cid:374)(cid:374)e(cid:272)ted to the r i(cid:374)put (this eli(cid:373)i(cid:374)ates the t(cid:396)ou(cid:271)leso(cid:373)e (cid:1005) 1 input combination) When the enable input c is asse(cid:396)ted, the lat(cid:272)h is said to (cid:271)e (cid:862)ope(cid:374)(cid:863) a(cid:374)d the path f(cid:396)o(cid:373) the d i(cid:374)put to the. Q output is t(cid:396)a(cid:374)spa(cid:396)e(cid:374)t whe(cid:374) the e(cid:374)a(cid:271)le i(cid:374)put c is (cid:374)egated, the lat(cid:272)h (cid:862)(cid:272)loses(cid:863) - the q output retains its last value. There are four propagation delay parameters for this d latch and you will measure them in your lab : {refer to slide 121 of the ppt notes for module 3 for the figure and details of the propagation delays. } There is a window of time around the falling edge of c when the d input does not change. The time prior to this edge that the d input remains stable is the setup time.