ELEG 4983 Lecture Notes - Lecture 5: Register Renaming, Register File
31 Jan 2017
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Lec 5 instruction level parallelism, handling read after. One instruction goes in as one is finished. To achieve more than 1 ipc more than 1 instruction per clock cycle must be fed into the. Read after right hazard meaning r1 must be written to before it can be read from in the second instruction. True dependency, nothing can be done to get rid of it. With normal 5 stage pipeline r2 is read in the first instruction in the id stage (4 stages before it is written to in the 2nd instruction). In a parallel process a write after read dependency (war) is of concern. War is called an anti-dependency, or false dependency, can be eliminated via register renaming. R2 value is used up until its value is changed. A change is distinguished by renaming the register in the instances after its been modified.
