ECS 154A Lecture Notes - Lecture 9: Shift Register, Logical Shift, Maurice Karnaugh
14 Jul 2016
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T flip-flops toggles its output on a rising edge, and otherwise keeps its present state. Since the toggle from high to low to high takes two clock cycles, the output frequency will be half of the clock frequency. Designing a t flip-flop (that toggles the output) from s-r flip-flops. Karnaugh maps for s-r flip-flops and t flip-flops, where q is the present state, and q" is the next state. To solve this we note what sr combination(s) will create each t next state for each q. If t = 0 and q = 0, then q" = 0. If q = 0 and q" = 0, then s = 0, and r is in either state. If t = 0 and q = 1, then q" = 1. If q = 1 and q" = 1, then r = 0, and s is in either state.
