ECS 154A Lecture Notes - Lecture 19: Eprom, Eeprom, Bit
2 Aug 2016
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Sram bit circuit: standby (the circuit is idle) = if the word line (wl) is not asserted, the access transistors m5 and m6 disconnect the cell from the bit lines. The two cross-coupled inverters formed by m1 m4 will continue to reinforce each other as long as they are connected to the supply: reading procedure. On the bl side, the transistors m4 and m6 pull the bit line logically set to 0): the bl and will have a small difference between them that reaches a sense amplifier. The higher the setting to 1 and bl to 0. This is similar to applying a reset pulse to an sr-latch, which causes the flip: applying the value to be written to the bit lines. If we wish to write a 0, we would apply a 0 to the bit lines, i. e. flop to change state.
