1) Design using VHDL with EDAPlayground, a 4 x 4-bit parallel multiplier using the correct
number of adder blocks - full-adders (FAs) and half-adders (HAs). This must include the
AND gates to generate the product terms and use the carry-save method with a ripple-
carry adder in the final row (CLA adder is not required in the last row).
a. You would need to use the RTL level design for the basic gates, i.e., AND,
OR, NOT gates. For the XOR gate, you can use either RTL level or
Structural level design (justify the choice). Then, FAs and HAs need to be
implemented using the structural level design. Finally, the final parallel
adder requires the structural level design for connecting the AND gates,
FAs and HAs.
b. Per each of the basic gates, consider the delay based on the architecture,
i.e., AND gates delay;
c. Show simulation results using EPWave by designing a dedicated testbench
(i.e., testbench.vhd) with different input values in the range of 0-15.
d. You should explain the design process and choices in a short report (up to 2
pages max). The report MUST include the EDAplayground link of the design.
2) Design in VHDL, using EDAPlayground, a 4-bit serial multiplier. You can choose either an
8-bit Adder, as shown in Fig. 1, in which, by relying on a CLK signal, the following operations
are repeatedly executed to obtain the final result:
1. Load R and D; Clear P to 0 (only the first time);
2. Add the partial product (r0 AND D) to P;
3. Shift R right 1 bit; Shift D left 1 bit;
4. Repeat from step 2 a total of 4 times.
