CSC258H1 Lecture Notes - Clock Signal, Gibbs Phenomenon, Truth Table
Document Summary
Reading from latches: need some sort of timing single. To signal the circuit when the output may be sampled. To differentiate btwn single high value and two high values in a row: clock signals regular pulse signal, where the high value indicates that the output of the latch may be sampled. Signal restrictions: what"s the limit to how fast the latch circuit can be sampled, determined by. Gibbs phenomenon: frequency = how many pulses occur per second, in hertz (hz) Star off with s = 0 and r = 1. If c = 1, the first nand gates invert those values, which get inverted again in the output. Setting s = 0 and r = 0, maintains the output value. Even if the inputs change, the low clock input prevents the change from reaching the second stage of nand gates.
