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Microprocessor%20Systems%202DP4%20Sample%20Exam%202013%20with%20solutions.pdf

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Department
Computer Engineering
Course Code
COMPENG 2DP4
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Joe Kim

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NAME______________________________ STUDENT NUMBER____________________ COMP ENG 2DP4 DAY CLASS Dr. J. Fortuna DURATION OF EXAMINATION: 3 Hours McMaster University SAMPLE Final Examination April 2013 This examination paper includes 16 pages and 5 questions. You are responsible for ensuring that your copy of the paper is complete. Bring any discrepancy to the attention of your invigilator. SPECIAL INSTRUCTIONS: Only McMaster approved calculators are permitted (Casio FX-991). Please show ALL work on the exam pages given. When the question is subdivided into a number of parts, the marks allocated for each section are indicated. This is a closed book examination. No reference materials of any kind are permitted. Pages 12 – 16 are provided for your reference. The distribution of marks is as follows (do not write in this box!): Marks Mark Question Available Obtained 1 30 2 10 3 15 4 10 5 10 Total 75 Page 1 of 16 NAME______________________________ STUDENT NUMBER____________________ Question 1. – Multiple Choice (30 marks) Choose the BEST answer from each of the following multiple choice questions and write the answer in the space provided. 1) B The operand of an instruction contains: a. The type of instruction to be executed b. Any data required by the instruction c. The address that the instruction must be executed at 2) A A relative branch: a. Sets the program counter to an offset from the program counter specified in the operand b. Sets the program counter to an absolute value specified in the operand c. Both a and b d. Neither a nor b 3) B In a jump instruction, the operand of the instruction must contain: a. Bits that represent where the instruction is to be executed b. Bits that represent how the program counter will be modified c. Neither a nor b 4) B When a previous arithmetic operation sets the carry bit: a. Either a BRA LTU or a BRA LEU will cause a branch to be taken b. A BRA GEU will cause a branch to be taken c. Neither a nor b 5) D On a PIC24, When a number is subtracted from itself, the status register indicates that: a. The carry bit is zero and the zero bit is zero b. The carry bit is zero and the zero bit is one c. The carry bit is one and the zero bit is zero d. The carry bit is one and the zero bit is one Page 2 of 16 NAME______________________________ STUDENT NUMBER____________________ 6) C A weak pull-up output on a PIC24 refers to the fact that: a. An internal transistor between the output pin and ground is turned partially on b. An internal transistor between the output pin and VDD is turned off c. An internal transistor between the output pin and VDD is turned partially on 7) B For an instruction that uses indirect addressing: a. The operand contains a value that is to be loaded into the program counter b. The operand contains a register that specifies a pointer to the data c. The opcode must be equal to the operand 8) C An open drain output on a PIC24 refers to the fact that: a. The output cannot be driven high b. The output can only sink current c. Both a and b In a switch-case implementation of a state machine, a transition condition is indicated 9) D by: a. A conditional statement that initiates a while( 1 ) loop b. A call to the next subroutine in the code c. A conditional statement that can modify the value of outputs that change in the state d. A conditional statement that can change the value of the state indicator variable 10) C Tri-state buffers are used: a. To eliminate the need for open-drain outputs b. To avoid having two or more inputs connected together c. To avoid having two or more outputs connected together d. To eliminate the need for weak pull-up outputs Page 3 of 16 NAME______________________________ STUDENT NUMBER____________________ 11) C When a MOV W0, [W1+W2] is used to implement storing to an array: a. W1 represents start and W2 represents the end addresses of the array b. Both W1 and W2 are set to the start address of the array c. W1 represents the address of the start of the array and W2 represents the array index 12) A A stack frame is used: a. To maintain local variables within a called routine b. To maintain local variables from the calling routine c. To maintain any values returned from the calling routine 13) D On a PIC24, each entry in the interrupt vector table: a. Contains the first line of code for the corresponding interrupt service routine b. Is an instruction that jumps to the beginning of the corresponding interrupt service routine c. both a and b d. neither a nor b 14) C A Multiply and Accumulate instruction provides a natural implementation for: a. A discrete convolution operation b. An IIR type filter c. both a and b d. neither a nor b 15) A Polled I/O reads new data is from an I/O device by: a. Monitoring the status of the device continuously and reading when the device is ready b. Calling the polling vector routine in the I/O vector table c. Jumping to the interrupt provided by the device and reading the device in the ISR Page 4 of 16 NAME______________________________ STUDENT NUMBER____________________ 16) B The conversion time of an Analog to Digital Converter provides a limit to: a. The resolution of the analog input b. The bandwidth of the analog input c. The maximum voltage of the analog input 17) A The conversion time of a Digital to Analog Converter: a. Typically does not depend on the number of bits of resolution b. Is typically linearly dependent on the number of bits of resolution c. Is typically linearly dependent on the maximum conversion value For a 16 bit Analog to Digital Converter with a 10V reference, a 300 micro volt change 18) B will affect : a. One output bit b. Two output bits c. Three output bits For a Successive Approximation Analog to Digital Converter, if Vin =4 volts and Vref = 5 19) A volts, the third most significant bit of the conversion will be a: a. Zero b. One c. Value that depends on the number of bits in the conversion 20) C On the PIC24, the timer prescalar value: a. Does not affect the rate of timer increments b. Is a multiplier of the rate of the timer increments c. Is a divisor of the rate of timer increments Page 5 of 16 NAME______________________________ STUDENT NUMBER____________________ 21) B On the PIC24, a setting larger starting value for TMR2 will: a. Increase the length of time that timer 2 will run before it signifies a “timeout” b. Decrease the length of time that timer 2 will run before it signifies a “timeout” c. Not affect the length of time that timer 2 will run before it signifies a “timeout” On a PIC24, an interrupt that occurs with the same priority as a currently executing 22) D interrupt: a. Will always interrupt the currently executing interrupt b. Will never interrupt the currently executing interrupt c. Will only interrupt the currently executing interrupt if it has a higher vector number d. Will only interrupt the currently executing interrupt if it has a lower vector number On the PIC24, the corresponding interrupt flag must be cleared at the beginning of the 23) B interrupt because: a. Other interrupts will be disabled until the flag is cleared b. The interrupt will be called again upon completion of the ISR c. The interrupt can never happen again until the flag is cleared For an 12 bit Successive Approximation Analog to Digital Converter with Vref = 10 volts 24) C and an input voltage of 2.5 volts, the output code will be: a. 0x600 b. 0x200 c. 0x400 25) C Averaging 4 consecutive input sample values is equivalent to: a. A Discrete Fourier transform with equal coefficients b. A convolution of the input with an impulse c. FIR filtering with equal coefficients d. IIR filtering with non-zero coefficients on previous output samples Page 6 of 16 NAME______________________________ STUDENT NUMBER____________________ 26) A A 16K x 16 memory system has a total capacity of: a. 262,144 bits b. 256,000 bits c. 16,384 bits 27) B Static RAM: a. Is too slow for use in a processor cache b. Is used in a processor cache because it can be accessed very quickly c. Is used as the main memory in a computer because it is very cheap to manufacture 28) A Dynamic RAM refers to the fact that: a. Each memory cell will eventually lose its stored value unless it is re-written b. Each memory cell will lose its stored value when the power is turned off c. Each memory cell will retain its value even when the power is turned off 29) D The data setup time for memory refers to: a. The time for which data must be at a constant value after chip select is asserted b. The time for which data must be at a constant value after the write is completed c. The time for which data must be at a constant value before it can be read from memory d. The time for which data must be at a constant value before it can be written into memory For a 20 bit address bus (labeled A19o A )0 a 3 to 8 decoder connected to A ,17 an16A 15 30) B will: a. Divide the address range from 0x00000 to 0x7FFFF into 8 equal parts b. Divide the address range from 0x00000 to 0x3FFFF into 8 equal parts c. Divide the address range from 0x00000 to 0x1FFFF into 8 equal parts d. Divide the address range from 0x00000 to 0xFFFFF into 8 equal parts Page 7 of 16 NAME______________________________ STUDENT NUMBER____________________ 0xFFFF Question 2. Consider the following memory system connected to a microprocessor as shown: 16-bit address bus (A0-A15) A14A13A 12 A15 A 10 RD WR A0 - A9 S2S 1 0 enables to /we selects inputs of all RAMs 3:8 Line Decoder Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 10 10 10 10 address address address address cs cs cs cs 0x7FFF we RAM #1 we RAM #2 we RAM #3 we RAM #4 0x7C00 0x7800 RAM #4 data data data data 0x77FF 0x73FF 0x6FFF RAM #4 8 8 8 8 0x6C00 0x6800 RAM #3 0x67FF 8-bit data bus 0x63FF 0x6000 RAM #3 (a) (2 marks) What is the capacity and organization of a RAM device in the system above ? RAM Capacity (in bits): ________8096________ RAM Organization: ___1K x 8_____ (b) (1 mark) How many unique 8 bit memory locations exist in this systANSWER: __4096_____ (c) (1 mark) How many memory locations can be accessed by the microprocessor? ANSWER: _8192____ (d) (1 mark) What is the total number of locations in the entire address space? ANSWER: ___65536____ (e) (1 mark) What percentage of the entire memory space cannot be accessed? ANSWER: ____87.5____ (f) Label the memory map given above showing: a. (1 mark) the maximum and minimum addresses
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