COE 328 Final: COE328 - Spring 2016 Final
31 Jan 2019
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Time limit: 2 hour 50 minutes examiner: r. sedaghat. Notes: closed book, no calculators, answer all questions in the space provided, circle your professor"s name and hand in these sheets, no questions during the exam. Name:_______________________: given the following logic circuit, derive its state table and state diagram. 1010110101 is applied to the x input of the circuit with initial sate 01, determine the resulting output sequence on z output. Name:_______________________: given is following state diagram with x as input and z as output: X=1 / z=0: indicate the model of the above state diagram. Hint; mealy or moor: design and draw the circuit. Name:_______________________: given the following circuit using a 1 bit adder and register. Sketch the correct output waveforms at cin, co, s and z in their proper time relationship to the following input waveforms. Note: both flip-flops are initially set as indicated.
