COE 758 Midterm: COE758 - Fall 2008 Midterm (Solutions)

• School: Ryerson University
• Department: Computer Engineering
• Course: COE 758
• Professor: All

Document Summary

Estimate the design of the direct mapped cache unit with the following specification: Direct-mapped cache controller is implemented in fpga with embedded block ram (bram) for the cache content. Cache unit communicates with the main memory based on the sdram module. Question 1. 1: to determine the miss penalty (time to replace the block in cache) for the worst case scenario (d-bit for the block to be replaced always=1) calculate the following: Bus clock period t (ns) =_________t= 1/ f bus = 1 / 133. 33 x10 = 7. 5 ns ______ [1] Block transfer time t bt(ns) =32 words * 7. 5 ns = 240 ns___________________ [1] Block replacement time (if d-bit =1) t br = (taddr +tbt)*2 = (80+240)*2 = 640 ns. Miss penalty t miss =_tbr + thit = 640ns + 10 ns =650 ns________________ [2] Tmiss = thit + (taddr + 32words * 7. 5 ns /2) *2 = 410 ns.