COE 818 Final: COE 818 Winter 2006 Final

• School: Ryerson University
• Department: Computer Engineering
• Course: COE 818
• Professor: All

Document Summary

Coe 818 final exam , april 24 , 2006. Convert to mips assembly, then nd the performance (total time) of the fol- lowing c code assuming: 1-ideal pipelining (no stalls and no start up time) 2- all instructions and data accesses are in cache (100% hit). Y[i] =y[i] + a*x[i]; (assume a, x[i], y[i] are 32 bits) Convert the above code to mips instructions for vector processing, and nd the performance in total time assuming the following:- 1- mips uses a vector processor with fully pipelined function units and vector registers of 128 elements. 3-all instructions are in cache (100% hit), data accesses use interleaved memory for load/store and are fully pipelined with no stalls. The following code runs in dlx architecture, fp alu op has latency= 3 cycles, Fp alu op to sd latency= 2 cycles and ld latency = 1 cycle. Find the following: all types of hazards, the performance of the above (cycles per loop ).