Fall 2013 ECE 304 Assignment 4 Page 1 of 1
Due: October 31 2013, 8:00 am in seminar or anytimebefore in ECE304 drop box
1) In a Pseudo-NMOS inverter, determine the width ratio of the transistor that produces a low output
voltage of 0.1V DD as logic “0” assuming µ =3µ n UsepON resistance approximation instead of
complete I-V equations for transistors to calculate the output voltage.
2) Sketch transistor-level circuit diagram of CMOS, pseudo-nMOS, and CVSL logic circuits that
implements the function: F = [A(B+C.(D+EG))]’
3) Calculate the dynamic power dissipated in a static CMOS DSP consisting of two million gates where
one quarter of the gates operate at full clock frequency and at nominal voltage and the rest of the gates
operate at half clock frequency and at 80% of nominal voltage. The average activity factor for all
gates is 20%, the clock frequency is 1 GHz, the nominal voltage is 1.8 V, and the average load
capacitor is 2 fF per gate.
4) Design an asymmetric 3-input NOR gate that favors a critical input over the other two. Choose the
transistor sizes in the pull-up network so that the