EECE 252 Study Guide - Verilog, Dxo Labs, Init
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-ledr : out std_logic_vector(17 downto 0)); component vga_adapter. --- component from the verilog file: clock : in std_logic; colour : in std_logic_vector(2 downto 0); x : in std_logic_vector(7 downto 0); y : in std_logic_vector(6 downto 0); plot : in std_logic; Vga_r, vga_g, vga_b : out std_logic_vector(9 downto 0); Vga_hs, vga_vs, vga_blank, vga_sync, vga_clk : out std_logic); library ieee; - 11 bit significant figure 1 for sign { the new location } - 11 bit significant figure 1 for sign. - the current location dx: signed(11 downto 0); - it is active low, so keep it high for operation resetn <= sw(17); -plot <= not key(0); vga_u0 : vga_adapter generic map(resolution => 160x120) ---- sets the resolution of display (as per vga_adapter. v variable p: particleset := ((xnew=>b000111011000, ynew=>b001010101000, process(clock_50) --- p(0) green clock => clock_50, colour => colour, x => x, y => y, plot => plot,
