Lab 4 prelab.pdf

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University of British Columbia
Electrical and Computer Engineering
EECE 252

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; use IEEE.STD_LOGIC_ARITH.all; --use IEEE.numeric_std.all; entity lab4_test is port( CLOCK_50: in std_logic; KEY: in std_logic_vector(3downto 0); SW : in std_logic_vector(17downto 0); LEDG: out std_logic_vector( 7downto 0); VGA_R, VGA_G, VGA_B: out std_logic_vector(9downto 0); VGA_HS : out std_logic; VGA_VS : out std_logic; VGA_BLANK : out std_logic; VGA_SYNC : out std_logic; VGA_CLK : out std_logic); endlab4_test; architecture rtl of lab4_test is component vga_adapter ---- Componentfrom the Verilog file: vga_adapter.v generic(RESOLUTION: string); port ( resetn : in std_logic; clock : in std_logic; colour: in std_logic_vector(2downto 0); x : in std_logic_vector(7downto 0); y : in std_logic_vector(6downto 0); plot : in std_logic; VGA_R, VGA_G, VGA_B: out std_logic_vector(9downto 0); VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic); end component; signal resetn : std_logic; signal x : std_logic_vector(7downto 0); signal y : std_logic_vector(6downto 0); --signal x_set : std_logic_vector( 7downto 0); --signal y_set : std_logic_vector( 6downto 0); signal colour: std_logic_vector(2downto 0); signal plot : std_logic; signal slowCLK : std_logic; begin resetn <=KEY(3); LEDG(0) <=slowCLK; -- DEBUGGINGPURPOSE vga_u0: vga_adapter genericmap(RESOLUTION =>"160x120") ---- Sets the resolution of display(as per vga_adapter.v description) port map(resetn =>resetn, clock =>CLOCK_50, colour=>colour, x =>x, y =>y, plot =>plot, VGA_R=>VGA_R, VGA_G=>VGA_G, VGA_B=>VGA_B, VGA_HS =>VGA_HS, VGA_VS =>VGA_VS, VGA_BLANK =>VGA_BLANK, VGA_SYNC =>VGA_SYNC, VGA_CLK =>VGA_CLK); -- Slows down the 50MHz clock. process( CLOCK_50) variable counter: unsigned( 19downto 0) :="00000000000000000000"; variable gen_clk : std_logic:='0'; variable clk_state : std_logic:='0'; begin if ( CLOCK_50='1') then if ( counter=14000) then counter:="00000000000000000000"; if ( clk_state ='0' ) then gen_clk :='1'; clk_state :='1'; else gen_clk :='0'; clk_state :='0'; endif; else counter:=counter+1; endif; endif; slowCLK <=gen_clk; end process; Process( slowCLK ) variablex_pos : std_logic_vector( 7downto 0); variable y_pos : std_logic_vector( 6downto 0); variablex_pos_old : std_logic_vector( 7downto 0) :="00111111"; variablex_pos_new : std_logic_vector( 7downto 0) :="00111111"; variable y_pos_old : std_logic_vector( 6downto 0) :="0110000"; variable y_pos_new : std_logic_vector( 6downto 0) :="0110000"; variablex_dir: std_logic:='1'; variable y_dir: std_logic:='1'; variable colour_set : std_logic_vector( 2downto 0); variable counter: std_logic_vector( 3downto 0) :="1010"; variablex_pos_old2: std_logic_vector( 7downto 0) :="01111001"; variablex_pos_new2: std_logic_vector( 7downto 0) :="01111001"; variable y_pos_old2: std_logic_vector( 6downto 0 ) :="0111100"; variable y_pos_new2: std_logic_vector( 6downto 0) :="0111100"; variablex_dir2: std_logic:='0'; variable y_dir2: std_logic:='0'; variable counter2: std_logic_vector( 3downto 0) :="1010"; type dstate is (eraseOld, stay, drawNew ); type bstate is ( ball_1, ball_2); variable drawState : dstate; variable drawState2: dstate; variable ballState : bstate :=ball_1; begin if ( slowCLK ='1') then if ( ballState =ball_1) then ballState :=ball_2; if ( counter=10) then counter:="0000"; drawState :=drawNew; elsif ( counter=0) then drawState :=eraseOld; counter:=counter+1; else
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