EECE 252 Study Guide - Verilog
Document Summary
- creates a getline component which gets input from this top entity and. - outputs to the vga adapter library ieee; use ieee. std_logic_1164. all; use ieee. std_logic_arith. all; entity lab_5 is port( Ledg : out std_logic_vector( 8 downto 0 ); Ledr : out std_logic_vector( 17 downto 0 ); Vga_r, vga_g, vga_b : out std_logic_vector(9 downto 0); -- the outs go to. --- component from the verilog file: clock : in std_logic; colour : in std_logic_vector(2 downto 0); x : in std_logic_vector(7 downto 0); y : in std_logic_vector(6 downto 0); plot : in std_logic; Vga_r, vga_g, vga_b : out std_logic_vector(9 downto 0); Vga_hs, vga_vs, vga_blank, vga_sync, vga_clk : out clk_in : in std_logic; x_out : out std_logic_vector( 7 downto 0 ); y_out : out std_logic_vector( 6 downto 0 ); Ledr_out : out std_logic_vector( 17 downto 0 ); plot_line : out std_logic end component; begin vga_adapter. v description)
