Lab 5 Prelab.pdf

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University of British Columbia
Electrical and Computer Engineering
EECE 252

-- Creates agetLine component which gets inputfrom this topentity and -- outputs to the VGA adapter library IEEE; use IEEE.STD_LOGIC_1164.all; useieee.std_logic_arith.all; entity Lab_5is port( CLOCK_50: in std_logic; KEY: in std_logic_vector(3downto 0); SW : in std_logic_vector(17downto 0); LEDG: out std_logic_vector( 8downto 0); -- debugging purpose LEDR: out std_logic_vector( 17downto 0); -- debugging prupose VGA_R, VGA_G, VGA_B: out std_logic_vector(9downto 0);-- The outs go to VGA controller VGA_HS : out std_logic; VGA_VS : out std_logic; VGA_BLANK : out std_logic; VGA_SYNC : out std_logic; VGA_CLK : out std_logic); end Lab_5; architecture rtl of Lab_5is component vga_adapter ---- Componentfrom the Verilog file: vga_adapter.v generic(RESOLUTION: string); port ( resetn : in std_logic; clock : in std_logic; colour: in std_logic_vector(2downto 0); x : in std_logic_vector(7downto 0); y : in std_logic_vector(6downto 0); plot : in std_logic; VGA_R, VGA_G, VGA_B: out std_logic_vector(9downto 0); VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic); end component; component getLine port( x_in1, x_in2: in std_logic_vector( 7downto 0); y_in1, y_in2: in std_logic_vector( 6downto 0); clk_in : in std_logic; x_out : out std_logic_vector( 7downto 0); y_out : out std_logic_vector( 6downto 0); LEDR_out : out std_logic_vector( 17downto 0); plot_line : out std_logic ); end component; signal x : std_logic_vector(7downto 0); signal y : std_logic_vector(6downto 0); signal x0: std_logic_ve
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