Lab 5 getLine.pdf

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University of British Columbia
Electrical and Computer Engineering
EECE 252

-- gets starting and end positions of the line and outputs the -- next position of the pixel to be drawn every clock cycle. library IEEE; use IEEE.STD_LOGIC_1164.all; useieee.numeric_std.all; entity getLine is port( x_in1, x_in2: in std_logic_vector( 7downto 0); y_in1, y_in2: in std_logic_vector( 6downto 0); clk_in : in std_logic; init : in std_logic; colour_in : in std_logic_vector( 2downto 0 ); x_out : out std_logic_vector( 7downto 0); y_out : out std_logic_vector( 6downto 0); plot_line : out std_logic; colour_out: out std_logic_vector( 2downto 0) ); end getLine; architecture rtl of getLine is begin process( clk_in ) variable dx : integer; variable dy : integer; variable temp: integer; variable sx : integer; variable sy : integer; variablex0: integer; variablex1: integer; variable y0: integer; variable y1: integer; variableerr: integer; variablee2: integer; variableinit_flag : std_logic:='0'; variableinitialized : std_logic:='0'; variable newP : std_logic; variable colour: std_logic_vector( 2downto 0) :="000"; variable done : std_logic:='0'; begin if ( clk_in ='1') then if (initialized ='0') then init_flag :=init; endif; if (init_flag ='1' ) then newP :='0'; colour:=colour_in; x0:=to_integer( unsigned(x_in1)); x1:=to_integer( unsigned(x_in2)); y0:=to_in
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