Lab 5.pdf

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University of British Columbia
Electrical and Computer Engineering
EECE 252

-- Creates agetLine component which gets inputfrom this topentity and -- outputs to the VGA adapter library IEEE; use IEEE.STD_LOGIC_1164.all; useieee.std_logic_arith.all; entity Lab_5is port( CLOCK_50: in std_logic; KEY: in std_logic_vector(3downto 0); SW : in std_logic_vector(17downto 0); LEDG: out std_logic_vector( 8downto 0); -- debugging purpose LEDR: out std_logic_vector( 17downto 0); -- debugging prupose VGA_R, VGA_G, VGA_B: out std_logic_vector(9downto 0);-- The outs go to VGA controller VGA_HS : out std_logic; VGA_VS : out std_logic; VGA_BLANK : out std_logic; VGA_SYNC : out std_logic; VGA_CLK : out std_logic); end Lab_5; architecture rtl of Lab_5is component vga_adapter ---- Componentfrom the Verilog file: vga_adapter.v generic(RESOLUTION: string); port ( resetn : in std_logic; clock : in std_logic; colour: in std_logic_vector(2downto 0); x : in std_logic_vector(7downto 0); y : in std_logic_vector(6downto 0); plot : in std_logic; VGA_R, VGA_G, VGA_B: out std_logic_vector(9downto 0); VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic); end component; component getLine port( x_in1, x_in2: in std_logic_vector( 7downto 0); y_in1, y_in2: in std_logic_vector( 6downto 0); clk_in : in std_logic; init : in std_logic; colour_in : in std_logic_vector( 2downto 0); x_out : out std_logic_vector( 7downto 0); y_out : out std_logic_vector( 6downto 0); --LEDR_out : out std_logic_vector( 17downto 0); plot_line : out std_logic; colour_out: out std_logic_vector( 2downto 0) ); end component; signal x : std_logic_vector(7downto 0); signal y : std_logic_vector(6downto 0); signal x0: std_logic_vector(7downto 0); signal y0: std_logic_vector(6downto 0); signal x1: std_logic_vector(7downto 0); signal y1: std_logic_vector(6downto 0); signal init_flag1: std_logic; signal colour_in1: std_logic_vector(2downto 0); signal colour_out : std_logic_vector(2downto 0); signal plot : std_logic; signal resetn : std_logic; signal x2: std_logic_vector(7downto 0); signal y2: std_logic_vector(6downto 0); signal x3: std_logic_vector(7downto 0); signal y3: std_logic_vector(6downto 0); signal init_flag2: std_logic; signal colour_in2: std_logic_vector(2downto 0); begin --colour<=SW(17downto 15); resetn <=KEY(3); vga_u0: vga_adapter genericmap(RESOLUTION =>"160x120") ---- Sets the resolution of display(as per vga_adapter.v description) port map(resetn =>resetn, clock =>CLOCK_50, colour=>colour_out, x =>x, y =>y, plot =>plot, VGA_R=>VGA_R, VGA_G=>VGA_G, VGA_B=>VGA_B, VGA_HS =>VGA_HS, VGA_VS =>VGA_VS, VGA_BLANK =>VGA_BLANK, VGA_SYNC =>VGA_SYNC, VGA_CLK =>VGA_CLK); get_line1: getLine port map( x_in1=>x0, y_in1 =>y0, x_in2 =>x1, y_in2 =>y1, init => init_flag1, colour_in =>colour_in1, clk_in =>CLOCK_50, x_out =>x, y_out =>y, plot_line =>plot, colour_out =>colour_out ); --get_line2: getLine port map( x_in1=>x2, -- y_in1 =>y2, -- x_in2 =>x3, -- y_in2 =>y3, -- init => init_flag2, -- colour_in =>colour_in2, -- clk_in =>CLOCK_50, -- x_out =>x, -- y_out =>y, -- plot_line =>plot, -- colour_out =>colour_out -- ); -- process( KEY(0)) variablex0V : integer:=5; variablex1V : integer:=10; variable y0V : integer:=5; variable y1V : integer:=95; variable colour_temp : std_logic_vector( 2downto 0); variableinit1: std_logic:='0'; variableinitialized : std_logic:='0'; variable reset_flag : std_logic; variablex2V : integer:=10; variablex3V : integer:=15; variable y2V : integer:=5; variable y3V : integer:=95; variableinit2: std_logic:='0'; variablex4V : integer:=15; variablex5V : integer:=20; variable y4V : integer:=5; variable y5V : integer:=95; variableinit3: std_logic:='0'; variablex6V : integer:=20; variablex7V : integer:=25; variable y6V : integer:=5; variable y7V : integer:=95; variableinit4: std_logic:='0'; variablex8V : integer:=25; variablex9V : integer:=30; variable y8V : integer:=5; variable y9V : integer:=95; variableinit5: std_logic:='0'; variablex10V : integer:=30; variablex11V : integer:=35; variable y10V : integer:=5; variable y11V : integer:=95; variableinit6: std_logic:='0'; variablex12V : integer:=35; variablex13V : integer:=40; variable y12V : integer:=5; variable y13V : integer:=95; variableinit7: std_logic:='0'; variablex14V : integer:=40; variablex15V : integer:=45; variable y14V : integer:=5; variable y15V : integer:=95; variableinit8: std_logic:='0'; variablex16V : integer:=45; variablex17V : integer:=50; variable y16V : integer:=5; variable y17V : integer:=95; variableinit9: std_logic:='0'; variablex18V : integer:=50; variablex19V : integer:=55; variable y18V : integer:=5; variable y19V : integer:=95; variableinit10: std_logic:='0'; type stateis ( start, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, done ); variable currentState : state :=start; begin if (falling_edge( KEY(0)) ) then case currentStateis when start => if ( SW(0) ='0') then currentState :=L1; reset_flag :='0'; else currentState :=start; reset_flag :='1'; endif; when L1=> if (
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