Lab 1 Converter.pdf

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University of British Columbia
Electrical and Computer Engineering
EECE 252

-- Lab 1Skeleton File library ieee; useieee.std_logic_1164.all; useieee.std_logic_arith.all; -- Each VHDLmodule has two parts: an "entity" part and an "architecture" -- part. The "entity" part describes the inputs and outputs of the -- module. The "architecture" part describes the function orstructure -- of the moduleitself. -- Below is theentity part of the converter. Theinputs are sw(2), -- SW(1), and SW(0), and the outputs are HEX0(6) downto HEX0(0). -- Note that the threeinputs SW(2), SW(1) and SW(0) are collectively referred to -- as the three bit bus SW. If SW="011", this means that SW(2)is -- 0(the first digit), SW(1)is 1(the second digit), and SW(0) is -- 1(the third digit). In addition, note that seven outputs are -- collectively referred to as HEX0. So if HEX0is "0110111", then -- HEX0(6) is 0(the first digit), HEX0(5) is 1(the second digit),etc. -- We need to use these names, since our"pin assignment"file has -- these signal names hardcoded. Don't change this forLab 1. entity converteris port( -- slide switches SW: in std_logic_vector(2downto 0); -- 7-segment display HEX0: out std_logic_vector(6downto 0)); end converter; -- Next is the architecture part of the converter. This will describe -- the function of the module. architecture behavioural of converteris begin -- There are many ways to describe combinational logicinVHDL, and -- we will see anumberof them in class. The method below is perhaps -- the most common, because itis fairly straightforward. -- The following line indicates the start of a"process". Fornow, you -- can think of a"process" as a"block of hardware". The
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