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CSC258H1 (8)

# CH 4 - Flipflops

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Department
Computer Science
Course
CSC258H1
Professor
Steve Engels
Semester
Winter

Description
SEQUENTIAL CIRUCITSLatchesSomething to consider o If multiple gates of these types are combined you can get more o Computer specs us terms like 8GB of Ram and 22GHz steady behavior processors o These circuits are called latchesRAMRandom Access Memory 8GB8 Billion ints o SR Latch behavior22 GHz22 billion clock pulses per secondAssume that S1 and R0 at start1 hertz1 operation per secondThe R input sets the output Q to 1 which sets the output o What does this mean in circuity Q to 0How do you use circuits to store valuesSetting R1 keeps the output Q at 1 which maintainsWhat is the purpo both output valuesse of a clock signalCurrently a particular input cause particular output o Consider a same input has 3 different outputs ex Tickle Me ElmoTwo kinds of circuits o Combinational Cirucits past materialCircuits where the output values are entirely dependent and predictable from the input values o Sequential Circuit newCircuits that depend on both the inputs and the previous state of the circuit Assume that S1 and R1 at start and then S set to 0Sequential circuitsThis sets output Q to 1 which sets the output Q to 0 o This creates circuits whose internal state can change over timethe same input values can result in different outputsSetting S1 keeps the output value Q at 0 which o Purpose memory values react to changing inputs maintains both output valuesCreating Sequential circuits o Essentially sequential circuits are a result of having feedback in the circuitNote how the circuit remembers its signal going from 10 or 01to 11 o Some gates dont have useful results when outputs are fed back on Q Q R S Q Q TT1TT1inputs 0 0 X X 1 1 A Q Q TT10 1 X X 1 0 0 0 0 1 0 X X 0 1 0 1 0 1 1 0 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 Going from 00 to 11 produces unstable behaviorA Q Q o SR Latch behavior TT10 0 0 0 1 1 1 0 1 1 1 1In these truth tables Q and Q represent the values of Q at a TT1time T and a point in time immediately after T1 o Others have more interesting characteristics which lend themselves to storage devicesA Q Q TT1 In this case the circuit remember previous output when going 0 0 1 from 10 or 01 to 00 0 1 1 SQ Q Q Q TT11 0 1 TT10 0 0 1 0 1 1 1 0 0 1 1 0 1 0 1 0 X X 0 1 1 1 X X 1 0 1 1 X X 0 0Going from 11 to 00 produces unstable behavior The output sginals dont change instantaneously A Q Q TT1o More on instability 0 0 1 0 1 0Unstable behavior occurs when a SR latch goes from 00 to 11 1 0 0 or a SR latch goes from 11 to 00 1 1 0The singals dont change simultaneously so the outcome o NAND and NOR feedback circuits unlike AND and OR which gets depends on which singal changes first stuck the output Q can be changed based on A T1 Because of the unstable behavior 00 is considered a forbiddenHowever gates like these that feed back on themselves could state in NANDbased SR latches and 11 is considered a center an unsteady state forbidden state in NORbased SR latches
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