CSC258H1 Study Guide - Instruction Register, Opcode, Machine Code

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Published on 20 Apr 2013
School
UTSG
Department
Computer Science
Course
CSC258H1
Professor
ASSEMBLY LANGUAGE
Intro to Machine Code
o Now that we have a processor, operations are performed by:
The instruction register, decoding each instruction according to
the opcode in the first 6 bits
The control unit sending a sequence of signals to the rest of the
processor, according to the opcode value passed in from the
o Only question remaining:
Hwere do these instructions come from?
How are they provided to the instruction memory?
Assembly language
o Each processor type has its own language for representing 32-bit
instructions as user-level code words
o Ex. C = A + B Store A in $t1, B in $t2, C in $t3
In Assembly Language instruction:
add $t3, $t1, $t2
In Machine Code instruction:
000000 01001 01010 01011 XXXXX 100000
Control Unit signals:
PCWrite = 0 PCWriteCond = 0
IorD = X
MemRead = 0, MemWrite = 0
MemtoReg = 0
IRWrite = 0
PCSource = X
ALUOp = 001 (add)
ALUSrcA = 1, ALUSrcB = 0
RegWrite = 1, RegDst = 1 (R-type)
Note: most of the time only one write signal is on
o Ex. Add 100 to value in PC and store it back into the PC
Operation used by Assembly to jump
Instruction is addi, the value 100 in instruction[15-0]
ALUSrcB is from Sign Extend, needed b/c the value
100 in instruction[15-0] is 16-bits, need 32-bits
to for ALU to operate on it
Control Unit signals:
PCWrite = 1 PCWriteCond = x
IorD = x
MemRead = 0, MemWrite = 0
MemtoReg = x
IRWrite = 0
PCSource = 1
ALUOp = 001 (add)
ALUSrcA = 0, ALUSrcB = 2
RegWrite = 0, RegDst = x
o Assembly language instruction is the lowest programmable language
One-to-one maping with a machine code language
o Many compilers translate their high-level program commands into
assembly, which are then converted into machine code and used by
the processor
Note: there are multiple types of assembly language, especially
for different architectures
MICROPROCESSOR WITHOUT INTERLOCKED PIPELINE STAGES (MIPS)
o Type of REDUCED INSTRUCTION SET COMPUTER (RISC) architecture
o Provides a set of simple and fast instructions
Compiler translates instructions into 32-bit instructions for
instruction memory
Complex instructions (multiplication) are built out of simple
ones by the compiler and assembler
o MIPS is REGISTER-TO-REGISTER
Every operation operates on data in registers
o MIPS provides 32 registers, several have secial values
Register 0 ($zero): value 0
always 0; can’t write into this register, only read
Register 1 ($st): reserved for the assembler
Register 2 3 ($v0, $v1): return values
Register 4 7 ($a0 a3): function arguments
Register 8 15, 24, 25($t0 $t9): temporaries
Register 16 23 ($s0 $s7): saved temporaries
Register 28 31 ($gp, $sp, $fp, $ra): memory and function
support
$sp is top of the stack, increments to 0
$ra is the return address, the address of a main program
when a subroutine complete, $ra is used to return to
the main program
$fp is the frame pointer
$gp is the global pointer
o Also three special registers (PC, HI, LO) that are not directly
accessible
HI and LO are used for multiplication and division, and have
special instruction for accessing them
MIPS Instructions
o Things to note about MIPS instructions
Instructions are written as: <instr> <parameters>
Each instruction is written on its own line
All instructions are 32-bits (4 bytes) long
Instruction addresses are measured in bytes, starting from the
instruction at address 0
o The following tables show the most common MIPS instructions, the
syntax for their parameters, and what operations they perform
o Arithemtic instruction
add = add 2 registers to a destination register
addi = add an immiedate value (an int) and a register to a
destination register
addu = add 2 registers w/ unsigned ints to a destination register
Instruction
Opcode/
Function
Synatx
Operation
add
100000
$d, $s, $t
$d = $s + $t
addu
100001
$d, $s, $t
$d = $s + $t
addi
001000
$t, $s, i
$t = $s + SE(i)
addiu
001001
$t, $s, i
$t = $s + SE(i)
div
011010
$s, $t
lo = $s / $t; hi = $s % $t
divu
011011
$s, $t
lo = $s / $t; hi = $s % $t
mult
011000
$s, $t
hi:lo = $s * $t
multu
011001
$s, $t
hi:lo = $s * $t
sub
100010
$d, $s, $t
$d = $s - $t
subu
100011
$d, $s, $t
$d = $s - $t
o Logical instructions
bit-wise logical operations
Instruction
Opcode/
Function
Synatx
and
100100
$d, $s, $t
$d = $s & $t
andi
001100
$t, $s, i
$t = $s & ZE(i)
nor
100111
$d, $s, $t
$d = ~($s | $t)
or
100101
$d, $s, $t
$d = $s | $t
ori
001101
$t, $s, i
$t = $s | ZE(i)
xor
100110
$d, $s, $t
$d = $s ^ $t
xori
001110
$t, $s, i
$t = $s ^ ZE(i)
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MIPS Instructions cont.
o Shift instructions
1st character: "s" = shift
2nd character: "l" or "r" = shift direction
3rd character: "a" or "l" = arthematic or logical
shift left logical == shift left arthematic (not in use)
4th (optional) character: "v" = a variable number of bits,
specified by $s
Instruction
Opcode/
Function
Synatx
Operation
sll
000000
$d, $s, a
$d = $t << a
sllv
000100
$d, $t, $s
$d = $t << $s
sra
000011
$d, $t, a
$d = $t >> a
srav
000111
$d, $t, $s
$d = $t >> $s
srl
000010
$d, $t, a
$d = $t >>> a
srlv
000110
$d, $t, $s
$d = $t >>> $s
Data movement instructions
o These instructions for operating on the HI and LO registers
Instruction
Opcode/
Function
Synatx
Operation
mfhi
010000
$d
$d = hi
mflo
010010
$d
$t = lo
mthi
010001
$s
hi = $s
mtlo
010011
$s
lo = $s
ALU instructions
o Note that for ALU instructions, most are R-type instructions
The six-digit codes in the table are therefore the function codes
(opcodes are 000000)
Exceptions are the I-type instructions (addi, andi, orri, etc.)
o Note all R-type instructions have an I-type equivalent
RISC architecures dictate that an operation doesn’t need an
instruction if it can be performed through multiple existing
operations
Ex. addi + div divi
Store the immediate value into a register first than divide
Example program
o A fibonacci sequence C code into assembly code
1. int fib(void) {
2. int n = 10;
3. int f1 = 1, f2 = -1;
4. while (n != 0) {
5. f1 = f1 + f2;
6. f2 = f1 f2;
7. n = n 1;
8. }
9. return f1;
10. }
o In assembly
Note: beq, j, and sb instructions will be touched upon later
1. # fib.asm
2. # register usage: $t3=n, $t4=f1, $t5=f2
3. # RES refer to memory address of result
4. FIB: addi $t3, $zero, 10 # initialize n=10
5. addi $t4, $zero, 1 # initialize f1=1
6. addi $t5, $zero, -1 # initialize f2=-1
7. LOOP: beq $t3, $zero, END # done loop if n==0
8. add $t4, $t4, $t5 # f1 = f1 + f2
9. sub $t5, $t4, $t5 # f2 = f1 - f2
10. addi $t3, $t3, -1 # n = n 1
11. j LOOP # repeat until done
12. END: sb $t4, RES # store result
o Making an asssmbly program
Assembly Lanauge programs typically have structure similar to
simple Python or C programs
Set aside registers to store data
Have sections of instructions that manipulate this data
Its always good to decide at the beginning which registers will
be used for what purpose
Control flow in assembly
o Not all programs follow a linear set of instructions
Some operations require the code to branch to one section of
the code or another (if/else)
Some require the code to jump back and repeat a section of
code again (for/while)
o For this, we have labels on the left-hand side that indicate the points
that the program flow might need to jump to
References to these points in the assembly code are resolved at
compile time to offset values for the program counter
o Branch instructions
Branch operations are key when implementing if statements
and while loops
The labels are memory locations, assigned to each lable at
compile time
Note: i is calculated as
(label (current PC + 4)) >> 2
In branch i-type instruction last 16 bits is the difference btwn
the branch-call location and the branch-to location
beq = branch if equals
bgtz = branch if greater than
blez = branch if lesser than or equals to
bne = branch if not equals
Note: branch if lesser than DNE, instead: beq, bgtz & blez
Instruction
Opcode/Fun
ction
Synatx
Operation
beq
000100
$s, $t, label
if ($s == $t)
pc += i << 2
bgtz
000111
$s, label
if ($s > 0)
pc += i << 2
blez)
000110
$s, label
if ($s <= 0)
pc += i << 2
bne
000101
$s, $t, label
if ($s != $t)
pc += i << 2
o Jump instructions
j = “jump”, for calling subroutines
similar to GOTO statements
if an assembly program doesn’t have jump statements,
the program will run from beginning to end sequentially
jal = “jump and link”, for calling functions
register $ra ($31) stores the address that’s used when
returning from a subroutine
jalr = “jump and link to register”
jr = “jump to register”, jump to address contain in register $s
usually for ending a subroutine by jumping to the return
address stored in $ra
note: jr and jalr are not j-type instructions
Instruction
Opcode/
Function
Synatx
Operation
j
000010
label
pc += i << 2
jal
000011
label
$ra = pc; pc += i << 2
jalr
001001
$s
$31 = pc; pc = $s
jr
001000
$s
pc = $s
o Comparison instructions
Comparison operation stores a:
1 in the dst register if the less-than comparison is true
0 in the dst register otherwise
Instruction
Opcode/
Function
Synatx
Operation
slt
101010
$d, $s, $t
$d = ($s < $t)
sltu
101001
$d, $s, $t
$d = ($s < $t)
slti
001010
$t, $s, i
$t = ($s < SE(i))
sltiu
001001
$t, $s, i
$t = ($s < SE(i))
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o If/Else statements in MIPS
Strategy for if/else statements;
Test condition, jump to if logic when condition is true
Otherwise, perform else logic block, and jump to first
line after if logic block
Ex. convert an If-Else block in C to assembly
If-Else block in C
1. if (i == j) {
2. i = i + 1;
3. } else {
4. j = j - 1;
5. }
6. j = j + i;
In Assembly version 1: If block after Else block
1. # $t1 = i, $t2 = j
2. main: beq $t1, $t2, IF # branch if (i == j)
3. addi $t2, $t2, -1 # j
4. j END # jump over if
5. IF: addi $t1, $t1, 1 # i++
6. END: add $t2, $t2, $t1 # j += i
In Assembly version 2: Else block after If block
1. # $t1 = i, $t2 = j
2. main: bne $t1, $t2, ELSE # branch if (i != j)
3. addi $t1, $t1, 1 # i++
4. j END # jump over else
5. ELSE: addi $t2, $t2, -1 # j--
6. END: add $t2, $t2, $t1 # j += i
Use flow charts to sort out the control flow of the code
o Ex. multiple If conditions
Multiple If-else in C
1. if (i == j || i == k) {
2. i++;
3. } else {
4. j--;
5. }
6. j = i + k;
In Assembly: branch statement for each condition
1. # $t1 = i, $t2 = j, $t3 = k
2. main: beq $t1, $t2, IF # cond1: branch if (i == j)
3. bne $t1, $t3, ELSE # cond2: branch if (i != k)
4. IF: addi $t1, $t1, 1 # if-body: i++
5. j END # jump over else
6. ELSE: addi $t2, $t2, -1 # else-body: j--
7. END: add $t2, $t1, $t3 # j = i + k
o Loops in MIPS
Loops usually implemented with the following syntax
For loop in C
1. for (<init> ; <cond> ; <update>) {
2. <for body>
3. }
For loop in Assembly
1. main: <init>
2. START: if (!<cond>) branch to EXIT
3. <for body>
4. UPDATE: <update>
5. jump to START
6. EXIT:
Ex. For loop
For loop in C
1. for (i = 0; i < 100 ; i++) {
2. j = j + i;
3. }
For loop in Assembly
1. # $t0 = i, $t1 = j
2. main: add $t0, $zero, $zero # set $t0 to 0
3. add $t1, $zero, $zero # set $t1 to 0
4. addi $t9, $zero, 100 # set $t1 to 100
5. START: beq $t0, $t9, EXIT # branch if (i == 100)
6. add $t1, $t1, $t0 # j = j + i
7. UPDATE: addi $t0, $t0, 1 # i++
8. j START
9. END:
while loops are the same, without the initalizaiton and update
sections
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Document Summary

Intro to machine code: now that we have a processor, operations are performed by: Microprocessor without interlocked pipeline stages (mips: type of reduced instruction set computer (risc) architecture, provides a set of simple and fast instructions. The instruction register, decoding each instruction according to. Compiler translates instructions into 32-bit instructions for the opcode in the first 6 bits instruction memory. The control unit sending a sequence of signals to the rest of the. Complex instructions (multiplication) are built out of simple processor, according to the opcode value passed in from the ones by the compiler and assembler: only question remaining: Assembly language: each processor type has its own language for representing 32-bit instructions as user-level code words, ex. C = a + b store a in , b in , c in . In assembly language instruction: add , , . Note: most of the time only one write signal is on. Regdst = 1 (r-type: mips is register-to-register.

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