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University of Toronto St. George
Electrical & Computer Engineering
Robert Brym

NAME_______________________ or ID#____________________ (in case pages g et detached) UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING MIDTERM EXAMINATION, FEBRUARY 2006 ECE243H1 S – COMPUTER ORGANIZATION Exam Type: D A. Moshovos, G. Steffan This is a type D exam. You are allowed to use the course textbook (any version), the lab manual (any version) and one double-sided A4 (or 8.5”x11”) sheet with notes. Calculators are not permitted. Last Name (Print): __________________ First Name: ________________________ Student Number: ___________________ Marks Max. Marks A 30 B 30 C 30 D 10 Total 100 Please: State your assumptions. Show your work. Comment your code. Use your time wisely as not all questions will require the same amount of time. If you think that assumptions must be made to answer a question, state them clearly. If there are multiple possibilities, comment that there are, explain why and then provide at least one possible answer and state the corresponding assumptions. There are 4 questions for a total of 100 marks. There are 1 double-sided pages in the exam. NAME_______________________ or ID#____________________ (in case pages g et detached) (A) [30 marks] Short Answer 1) Byte Order [6 marks] Assume that D0 is initializ$A1B2C3D4 before each of the following three instruction pairs executes . Give the value (in hex) of the least-significant byte of D1 after each of the following pairstructions have execute d, for both little and big endian machines (i.e., give only one value for each box): Little Endian Big Endian Move.l d0,$1000 $D4 $D4 Move.l $1000,d1 Move.w d0,$1000 $C3 $D4 Move.b $1001,d1 Move.l d0,$1000 $B2 $D4 Move.w $1002,d1 2) [6 marks] Assuming the following initialization: a0 = $00050000 d0 = $00000120 Write the effective address (i.e., the memory address accessed) of the destination (in hex) for each of the following, assuming the initialization above for each row (ie., all rows are independent): Insddcion Effective add.b d0,$a0 $a0 (the hex value) add.w d0,-12(a0) $4FFF4 add.l d0,-(a0) $4FFFC add.w d0,(a0)+ $50000 3) [6 marks] The following 68K assembly sequence: foo cmp.l d0,d1 bgtboo sub.l d d0, boo sub.l d1,d0 implements one the following C statements: (a) if (a > b) { b = b – a; } else {b = b – 2*a; } (b) if (b > a) { b = b – a; } else {b = b – 2*a; } (c) if (a == b) { b = a – b; } else { b = b – a; } (d) if (a > b) { a= a – b; } else { a= b – a; } (e) None of the above Which one? Circle your answer. Figuring out which registers a and b map to is part of the question. NAME_______________________ or ID#____________________ (in case pages g et detached) 4) [6 marks] Assume the following configuration of a serial connection: 20K BAUD (bit cells per second), 8 bits including one parity bit, even parity, 1 stop bit. a) If I transmit the ASCII encoding for 'C' (1000011 in binary), what bit sequence would I expect to receive for the frame? I.e., fill in the signal diagram below between the idle periods, clearly showing zeros and ones. Time Data 1 (idle) (idle) Wire: 0 Frame First is the START BIT. Then the 7 data bits for C starting from bit 0, then the parity which is 1 so that all the number of ones sent is even and finally the stop bit: 10 bits total: 0110000111 b) What is the effective data rate of this connection? Each 7 bits of actual data needs an additional 3 bits during transmission (start/stop/parity bits). Hence 20000 / 10 * 7 = 14000 bits/sec. Answers with 8 data bits will be considered correct and so will be answers with 20K = 1024*20. 5) [6 marks] While we have not discussed this in our lectures, in C one might declare the following array of pointers to integers: int *array[100]; Assuming the array has already been initialized, give the assembly instructions to implement the following statement: x = x + *(array[i]); Assume the following: x is in d0; i is in d1; ARRAY is a label defining the base address of array; an int is a long word. add.l d1, d1 ; i = 2 * i add.l d1, d1 ; i = 4 * i movea.l #ARRAY, a0 ; a0=base address adda.l d1, a0 ; a0 = address of array[i] movea.l (a0),a0 ; a0 = array[i] add.l (a0), d0 ; x = x + *array[i] NAME_______________________ or ID#____________________ (in case pages g et detached) (B) [30 marks] Memory Mapped I/O Consider a motor controller device (called MC) which allows you to turn on and off eight motors, and also to read up to eight binary sensors. MC responds to two memory mapped locations: MCOOR ($ffffabc0), the on/off register, which decides whether each motor is on or off. For example, if MCOOR bit 2 is a zero, then motor number 2 will be off; if MCOOR bit 2 is a one, then motor number 2 will be on. MCS ($ffffabc2), the sensor input pins, which allows the cpu to read a binary value from each of the eight sensors. For example, the input from sensor 2 will be on MCS bit 2. a. [4] Give two assembly directives that declare the memory mapped locations MCOOR and MCS. MCOOR equ $FFFFABC0 MCSeq $FFFFABC2 b. [4] Give one instruction that turns odd motors on (1,3,5,7), and even motors off (0,2,4,6) . move.b #$aa, MCOOR c. [6] Give two instructions that together will loop until sensor number 5 is a one: loop btsb.b #5,MCS beloop d. [6] Give two instructions that together “connect” the sensors directly to their respective motors. For example, when sensor number 3 becomes a one, motor number 3 turns on, and when sensor number 3 becomes a zero, motor number 3 turns off. loop move.b MCS, d0 move.b d0, MCOOR braloop e. [10] Using only the components shown below (and some wiring), implement the circuitry for bit 2 of MC (by filling in one of the figures on the next page). Decoder Example: Output is a one when the N Match 1 input address matches $abcde Match 1 the specified address $abcde Multiplexor Tri-State Buffer Or gate Inverter in0 in1 enable select And gate MUX
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