EECS 2021 Study Guide - Quiz Guide: Instrumental Case, Clock Signal, Speedup

• School: York University
• Department: Electrical Engineering and Computer Science
• Course: EECS 2021
• Professor: Mokhtar Aboelaze

Document Summary

1. 2: performance via pipelining, make the common case fast, design for moore"s law, dependability via redundancy, hierarchy of memories, use abstraction to simplify design, performance via prediction, performance via parallelism. No. instructions(p1) = 30 109 /1. 5 = 20 109. No. instructions(p2) = 25 109 /1 = 25 109. No. instructions(p3) = 40 109 /2. 2 = 18. 18 109: cpinew = cpiold 1. 2, then cpi(p1) = 1. 8, cpi(p2) = 1. 2, cpi(p3) = 2. 6. Cpi/time, then f (p1) = 20 109 1. 8/7 = 5. 14 ghz f (p2) = 25 109 1. 2/7 = 4. 28 ghz f (p1) = 18. 18 109 2. 6/7 = 6. 75 ghz. Total time p1 = (105 + 2 105 2 + 5 105 3 + 2 105 3)/(2. 5 109 ) = Total time p2 = (105 2 + 2 105 2 + 5 105 2 + 2 105 2)/(3 109 ) = 1. 14. 1 clock cycles = cpi fp no.