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Information Technology
ITEC 1000
Peter Khaiter

Focused Stuff Final Review For Itec 1000 Theories Data Representation: 1. Data formats:  Proprietary formats • Unique to a product or company • E.g., Microsoft Word, Word Perfect  Standards (evolve in two ways): • Proprietary formats become de facto standards (e.g., Adobe PostScript) • Invented by an international standard organization (e.g., Motion Pictures Experts Group, MPEG) Type of Data Standard(s) Alphanumeric Unicode, ASCII, EDCDIC Image (bitmapped)  GIF (graphical image format)  TIF (tagged image file format)  PNG (portable network graphics) Image (object) PostScript, JPEG, SWF (Macromedia Flash), SVG Outline graphics and fontsPostScript, TrueType Sound WAV, AVI, MP3, MIDI, WMA Page description PDF (Adobe Portable Document Format), HTML, XML Video Quicktime, MPEG-2, RealVideo, WMV Alphanumeric Data:  Characters (r, T), number digits (0..9), punctuation (!, ;), special purpose characters ($, &)  Four codes/standards to represent letters and numbers: • BCD (Binary-Coded Decimal) • Unicode • ASCII (American Standard Code for Information Interchange) • EBCDIC (Extended Binary Coded Decimal Interchange Code) ASCII Features:  Developed by ANSI (American National Standards Institute)  Defined in ANSI document X3.4-1977  7-bit code th  8 bit is unused (or used for a parity bit or to indicate “extended” character set)  2 = 128 different codes  Two general types of codes: • 95 are “Printing” codes (displayable on a console) • 33 are “Control” codes (control features of the console or communications channel)  Represents • Latin alphabet, Arabic numerals, standard punctuation characters • Plus small set of accents and other European special characters (Latin-I ASCII)  Magnetic stripe reader: alphanumeric data from credit cards  Voice  Digitized audio recording common but conversion to alphanumeric data difficult  Common Control Codes:  CR 0D carriage return  LF 0A line feed  HT 09 horizontal tab  DEL 7F delete  NULL 00 null EBCDIC:  8-bit code  Developed by IBM  IBM and compatible mainframes only  Rarely used today (common in archival data) • Character codes differ from ASCII  Conversion software to/from ASCII available Unicode:  Most common 16-bit form represents 65,536 characters  ASCII Latin-I subset of Unicode • Values 0 to 255 in Unicode table  Multilingual: defines codes for • Nearly every character-based alphabet • Large set of ideographs for Chinese, Japanese and Korean • Composite characters for vowels and syllabic clusters required by some languages  Allows software modifications for local-languages 2. C.P.U Components Components of the CPU (1 of 2)  ALU (arithmetic logic unit) • Performs arithmetic and logic operations (data changed) • Arithmetic: add, subtract, multiply, divide, etc. • Logic: AND, OR, NOT, Shift, etc. • Data held temporary  CU (control unit): functions • performs fetch/execute cycle • Accesses and retrieves program instructions from the memory and issues commands to the ALU • Moves data to and from CPU registers and other hardware components (no change in data)  Registers • Example: Program counter (PC) or instruction pointer determines next instruction for execution  Program counter (instruction pointer) • Contains the address of the current or next instruction • Normally instructions are executed sequentially  Memory management unit • Supervises fetching of instructions and data from memory • I/O Interface • Provides mechanism for input/output of data • sometimes combined with memory management unit in a single Bus Interface Unit Concept of Registers:  Single storage locations within the CPU used for a particular purpose  Used to hold a binary value temporarily  Manipulated directly by the Control Unit  Each register is wired within the CPU directly (no address needed) for specific function  Size in bits or bytes (not MB like memory) Can hold data, an address or an instruction Registers: what they do  Hold data being processed  Hold instruction being executed  Memory or I/O address being accessed  Keep status of the computer  Conditional branch instructions General-Purpose Registers:  User-visible registers  Part of ALU  Accumulators  Typically several dozen in modern CPUs (R0, R1,…)  Hold data of arithmetic operations  Hold intermediate results or data values, e.g., loop counters  To transfer data between different memory locations and between I/0 and memory Special-Purpose Registers:  Part of CU  Program Counter Register (PC) (instruction pointer) • Holds address of the currently executed instruction  Instruction Register (IR) • Holds the actual instruction being executed  Memory Address Register (MAR) • Holds the address of a memory location  Memory Data Register (MDR) • Holds the actual data value from location specified in MAR  Flags (one-bit register) to track special conditions like arithmetic carry and overflow, power failure, internal computer error  Status Registers • Several flag registers grouped together Accumulator: A dedicated register (or set of registers) in the CPU used for the actual manipulation of data Computer Buses  Group of electrical conductors (wires) for carrying signals from one location to another • Line: each conductor (or wire) in the bus  The physical connection that makes it possible to transfer data from one location in the computer system to another  4 kinds of signals • Data (alphanumeric, numerical, instructions) • Addresses • Control signals Power (sometimes)  Connect CPU and Memory  I/O peripherals: on same bus as CPU/memory or separate bus  If connect CPU, Memory and I/O modules in the same Physical package, called backplane • Also called system bus or external bus • Example of broadcast bus • Common method of connecting CPU, Memory and I/O modules: to a printed circuit board called motherboard Types of Buses (1 of 2)  Point-to-point  When connect plug-in devices, called ports  Multipoint: to connect several points together Bus Interface  Bus interface bridges: provide communication between different buses  Special buses provide interconnections within the CPU chip  Buses that form the backplane • External CPU bus • Peripheral control interface (PCI) bus • Accelerated graphic processor (AGP) • Industrial standard architecture (ISA) Bus Characteristics  Protocol • Documented agreement for communication • Specification that spells out the meaning of each line and each signal on each line  Throughput, i.e., data transfer rate in bits per second  Data width in bits carried simultaneously  Distance between two end points  Type of signals: unique/specialized or shared  Addressing capacity  Etc. Data Bus  Carries data between the CPU and memory or I/O devices  Bi-directional • Data transferred “out of” the CPU for write operations • Data transferred “into” the CPU for read operations  Typical sizes: 8, 16, 32, 64 lines  Signal names: D0, D1, D2, D3, etc. Address Bus  Carries an address from the CPU to Memory or I/O devices  Unidirectional • The address is always supplied by the CPU • (There is one exception to this, which we’ll discuss later.)  Typical sizes: 16, 20, 24 lines  Signal names: A0, A1, A2, A3, etc. Control Bus  Collection of signals for coordinating CPU activities  Each signal has a unique purpose  Typical sizes: 10-20 lines  Signals are output, input, or bi-directional  Typical signals • /RD (read) • /WR (write • CLK (clock) • /IRQ (interrupt request) • etc. PCI Bus  32- or 64-bit backplane  Interconnects: • CPU • Plug-in I/O (serial and parallel ports, sound cards, disc drives  Lines are non-specialized: carry addresses and data, labeled AD00 to AD31 (or AD63)  Additional lines: control and power lines Bus Characteristics:  Data width in bits carried simultaneously  Throughput, i.e., data transfer rate in bits per second  Topology: Point-to-Point vs. Multipoint  Parallel (simultaneous transfer i.e., individual lines for each bit of data, address and control) vs. Serial (sequential transfer on a single data line)  Use: internal (e.g., within CPU) vs. external  Distance: short (parallel)  Protocol External Interface Buses and Ports:  Peripherals - external I/O devices  Port – a connector at the end of the bus to connect a peripheral device  Port controller – general control for the port • Connected to standard buses, e.g., PCI or ISA  Device control is built into a controller within device and into computer software program (device drivers)  Device drivers – built into operating system or supplement to it  Types of external ports: • Parallel • Serial • High-speed general interface bus port Parallel port:  Originally: point-to-point bus for a single type of device  No addressing required  To connect printers  Control lines for printer-specific signals  Recent version IEEE 1284 allows sharing of multiple devices SCSI - Small Computer System Interface:  Parallel bus  Connects CD-ROM, HD, Tape, Scanner  Provides addressing for each device  Designed to be “daisy chained” (each device is plugged into the previous device)  Supports multiple devices from a single SCSI port Serial port:  RS-232C • Data transferred using a single data line for each direction • A number of control lines • Does not contain any address line • A single bus to connect a single device  RS-422 • Faster version of RS-232C • Used to connect terminals, modems, mice, network interfaces Universal Serial Bus – USB  Replaces standard serial port  Much faster: transfer rate – up to 480 Mega bits/sec  Multipoint bus uses hierarchical connection system  Hubs provide multiple connection points for I/O devices (up to 127 devices)  Data are transferred in packets: • Device identifier • Small set of data • Cannot tie up the system • Delivered at regular time intervals – isochronous data transfer USB:  Multipoint bus • Hubs provide multiple connection points for I/O devices • Supports 127 devices • 4 lines: • A single data pair (to carry data, address, control information) • 2 lines - power FireWire (  Serial multipoint bus  Designed for extremely fast data transfer – up to 3.2 Gigabits/sec  FireWire devices can be “daisy-chained” or connected together with hubs  Cable of two data pairs and an optional pair of power lines  Each segment of the bus can handle up to 63 devices  Each device controller is independent, no host bus controller is required  Devices can communicate with each other without a computer • Control capabilities must be built into every I/O module USB and FireWire (IEEE 1394):  Both serial, multipoint bus specifications  Add/remove devices w/o powering down  Packet protocol for isochronous data transfer • Isochronous: delivery at regular time intervals • Guarantee specified throughput USB vs. FireWire:  USB: slow to medium speed data transfer applications, i.e., storage devices • 12 Mbits/sec  USB-2: high-speed data transfer • 480Mbits/sec  FireWire: high-speed data transfer, i.e., full motion video with sound • 400 Mbits/sec to 3.2 Gbits/sec. Types of I/O:  Programmed I/O this one  Interrupt-driven I/O  Direct memory access (DMA) Programmed I/O (1 of 3)  I/O module connected to a pair of I/O registers in CPU via bus  Transfer: one word at a time  Input: I/O device I/O module I/O register AR under program control  Output: AR I/O register I/O module I/O device  In practice: multiple I/O devices connected to CPU 2  I/O data and address registers in CPU: work similarly to MAR and MDR  Address information must be sent with the I/O instruction in the address field  Requires full instruction fetch/execute cycle for each word data transfer  Very slow   Primary use: • keyboards • communication with I/O modules to control I/O operations (see DMA)  Interrupt-driven I/O Interrupts:  Signal that causes the CPU to alter its normal flow of a program/instruction execution • frees CPU from waiting for events • provides control for external input  Examples • unexpected input • abnormal situation • illegal instructions • multitasking, multiprocessing  Provided by special control lines to CPU • Called interrupt lines • In modern PCs: up to 32 labeled IRQ0..IRQ31 • Transmits message called interrupt • Causes computer to suspend program execution and jump to interrupt processing program Interrupt Terminology:  Servicing the interrupt • suspends program in progress • saves pertinent information including last instruction executed and data values in registers in the PCB (process control block) • branches to interrupt handler (routine) • After interrupt routine is complete, it returns control to the interrupted program, all original register values are restored Saving Registers:  For the interrupted program to resume, the CPU status and data registers must be saved (because they will change during the ISR)  They are saved before the ISR executes  They are restored after the ISR executes  They are saved either • On the stack (a special area of memory to temporarily hold information), or In a process control block (PCB) Use of Interrupts:  As an external event notifier  As a completion signal  As a means of allocating CPU time As an abnormal event indicator Interrupts for External Events:  An interrupt signal occurs when an “external event” occurs in a device – an event that requires the CPU’s attention  E.g., • Keyboard: a key has been hit (the ISR reads the code for the key) • Notebook computer cover: the cover is closed (the ISR puts the computer in standby mode) Interrupts for Completion Signals:  An interrupt signal occurs when a device has completed an operation – and the CPU should know about it  E.g., • Printer: the output buffer is empty (the CPU can send more data) • Scanner: a data transfer is complete (the CPU/application can proceed to process the image data) Interrupts for Allocating CPU Time:  Useful on multi-tasking systems – systems that can execute more than one program at a time  E.g., • A timer is programmed to interrupt the CPU every 100 µs (for example) • The ISR is a “dispatcher program” • Execution switches to another program (for 100 µs), etc. Interrupts for Abnormal Events:  An interrupt signal occurs when an abnormal event occurs that needs immediate system attention  E.g., • A heat sensor near the CPU chip – if the temperature is too high, an interrupt is generated, the ISR activates the fan near the CPU chip Multiple Interrupts:  In a real computer system • Many I/O devices • Multiple interrupts occur  Identifying devices caused interrupt by: • Polling (checking for input in rotation) • Vectored interrupts (include address of interrupting device as part of the interrupt)  Interrupt priorities • Loss of data vs. task completion  Maskable (disabled) interrupts Direct Memory Access:  Used for high-speed data transfers between an I/O device and memory in blocks  During the transfer, the CPU is not involved  Typical DMA devices: • Disk drives, tape drives  Remember (Table in slide 4) • Keyboard data rate à 0.01 KB/s (1 byte every 100 ms) • Disk drive data rate à 2,000 KB/s (1 byte every 0.5 µs) Conditions Required for DMA: • The I/O interface and memory must be connected • The I/O module must be capable of reading and writing to memory • Conflicts between the CPU and the I/O module must be avoided  Remark: application program requests I/O service from operating system • privileged instructions (i.e., only operating system software is allowed to access I/O instructions and procedures) How it works?  The CPU “prepares” the DMA operation by transferring information to a DMA controller (DMAC): • Location of the data on the device • Location of the data in memory • Size of the block to transfer • Direction of the transfer • Mode of transfer (burst, cycle steal) Stack Instructions:  Stack instructions • LIFO method for organizing information • Items removed in the reverse order from that in which they are added Direct, Absolute Addressing:  Direct: data is reached directly from the address in the instruction  Absolute: address in the instruction field is the actual memory location being addressed Additional Addressing Modes:  Programmer-accessible registers • Provide faster execution with register-based instructions  Alternatives to absolute addressing • Allow larger range of addressable memory • While using a reasonable number of bits for the address field  Alternatives to direct addressing • Facilitate writing certain types of programs • Example: loops that use index to address different entries in a table or array. Register Addressing:  Does not require a memory access • Contents of the source register is directly moved to the destination register • Faster execution as memory is not accessed • Practical application: frequently used data to be loaded from memory into registers and left there  Implemented directly as part of the CPU • All registers are located in the CPU (as a part of ALU or a separate register unit) Active- Area Memory.  Code executes in a small area of memory that changes as program proceeds  Well-written code • Small modular subroutines and procedures • Local variables • Conditional branches. Two Alternatives to Absolute Addressing:  Base register addressing  Relative addressing  Both provide starting address and an offset or displacement from the starting point • Starting address in register or program counter • Offset: address in the instruction  Programming advantage: permits to move the entire program to a different location in memory without changing any of the instructions (i.e., relocatability). Base Register Addressing:  Base register set to initial address • Hardware design: special/separate register or general-purpose registers • Generally large t
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