EL ENG 42 Study Guide - Final Guide: Academic Dishonesty, Logic Gate, Linear Circuit

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8 Jan 2019
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Academic dishonesty policies will be enforced: the sta wishes you the best of luck, both on this exam and in all your future endeavors. I have read all of the above instructions and agree to comply with them. All of the work on this exam is my own, and i had no prior knowledge of the exam contents. The logic gates and cmos circuit look like they"re about to commence battle. Frustrated at how inaccurate all our linear diode models have been, john decides to cook up another one. The zener diode below has a linear on characteristic and a breakdown voltage vb like any other, but it is modeled as a capacitor cd when it is reverse-biased, or off. id (a) 1 vd (v) (a) (3 points) let"s rst analyze the diode in its forward-bias (on) mode. Label the directions of vd and id. (b) (3 points) john attaches this diode to a circuit as shown below.