MGMT 1000 Chapter Notes - Chapter 17: Memory Address Register, Address Decoder, Computer Memory
MGMT 1000 Chapter 17 Notes – Summary
Introduction
• Using this technique, the addressing capability of the computer is determined by the
size of the register.
• For example, a computer with 64-bit registers could address 264 addresses if the MAR
were wide enough.
• Such an extension would suggest that the MAR
• Thus the actual memory capacity is normally at least as large as the instruction address
field, but it may be much larger.
• There is a brief discussion of simple addressing methods.
• Additional, more sophisticated addressing methods are presented in Supplementary.
• Ultimately, the width of the MAR determines the maximum amount of addressable
memory in the computer.
• Today, a typical memory address register will be at least 32 bits wide, and probably
much wider.
• Many modern CPUs support 64-bit memory addresses.
• A 32-bit memory address allows a memory capacity of 4 gigabytes (GB) (4 × 109 byte-
size spaces)
• Whereas 64 bits allows a memory capacity of 16 × 1018 bytes (16 exa bytes or 16 billion
gigabytes).
• In modern computers, the ultimate size of memory is more likely limited by physical
space for the memory chips.
• By the time required to decode and access addresses in a large memory, rather than by
the capability of the CPU to address such a large memory.
• Of course the size of memory also affects the speed of access.
• The time needed for the address decoder to identify a single line out of four billion is
necessarily larger than that required for a memory that is much smaller.
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