MGMT 1050 Chapter 18: MGMT 1050 Chapter 18 Notes
MGMT 1050 Chapter 18 Notes – Summary
Introduction
Fetch-Execute Cycle Timing Issues
• Each instruction requires a sequence of fetch-execute cycle steps, and the program
requires the execution of a sequence of these instructions.
• Thus, the keys to increased performance must rely on methods that reduce the number
of steps in the fetch-execute cycle or reduce the time required for each step in the cycle.
• Ultimately, reduce the time for each instruction in the program.
• As a first step, consider the problem of controlling the timing of each step in the fetch-
execute cycle to guarantee perfect CPU operation, to assure that each step the previous
step, in perfect order, as quickly as possible.
• There must be enough time between steps to assure that each operation is complete
and that data is where it is supposed to be before the next step takes place.
• As you saw most steps in the fetch-execute cycle work by copying, combining, or moving
data between various registers.
• When data is copied, combined, or moved between registers, it takes a short, but finite,
aout of tie for the data to settle dow i the ew register, that is, for the results
of the operation to be correct.
• This occurs in part because the electronic switches that connect the registers operate at
slightly different speeds.
• Were atually talkig illioths of a seod here!
• Also, design allowances must be made for the fact that some operations take longer
than others
• For example, addition takes more time than a simple data movement.
• Even more significant is the amount of time that it takes for the address stored in the
MAR to activate the correct address in memory.
• The latter time factor is due to the complex electronic circuitry that is required to
identify one group of memory cells out of several million or billion possibilities.
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