EE 2731 Chapter : 74ls138
Document Summary
The lsttl / msi sn54 / 74ls138 is a high speed 1-of-8 decoder / This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel ex- pansion to a 1-of-24 decoder using just three ls138 devices or to a 1-of-32 decoder using four ls138s and one inverter. The flatpak version has the same pinouts (connection diagram) as the dual in-line package. = 40 a high/1. 6 ma low: the output low drive factor is 2. 5 u. l. for military (54) and 5 u. l. for commercial (74) The ls138 is a high speed 1-of-8 decoder/demultiplexer fabricated with the low power schottky barrier diode process. The decoder accepts three binary weighted inputs (a0, a1, a2) and when enabled provides eight mutually exclusive active. The ls138 features three enable in- puts, two active low (e1, e2) and one active high (e3). All outputs will be high unless e1 and e2 are low and e3 is.
