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Chapter

Lab Report 4


Department
Electrical Engineering
Course Code
EE 2731
Professor
All

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Student name: Charles Thompson
Student name: Tyler Reynolds
Section: 4 Group: 4
Experiment 4 Flip-Flops
Construct a SR latch with an enable with a single 74LS00, construct a D latch by
modifying the SR latch and construct a master-slave JK flip-flop with two 74LS00
and one 74LS10.
SR-Latch
Digital Inputs: S’, R’ and C
Data Inputs: S’ and R’
Select Lines: S1, S2 and S3
Clock: C
Digital Output:
Q and Q’
D-Latch
Digital Inputs: D and C
Data Inputs: D
Select Lines: S1 and S2
Clock: C
Digital Output:
Q and Q’
Master Slave-JK Flip-Flop
Digital Inputs: J, K and CLK
Data Inputs: J and K
Select Lines: S1, S2 and Pulser
Clock: CLK
Digital Output:
Q and Q’
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