EE 2731 Chapter : E8G16
Document Summary
This experiment will introduce you to the design of a controller circuit used to control 3 shift registers. The controller will be used to make the shift register transfer data between themselves, in both parallel and serial forms. Sr0, sr1, sr2, & sr3 from switches (sw3 sw0); Digital output: sr1(led0 led3), sr2(led5), & sr3(led7) // additional comments: module shiftreg( input wire startstop, input wire clock, input wire [3:0] load, output reg [3:0] sr2, output reg [3:0] sr3 output reg [3:0] sr1, // internal constraints // parameter size = 3; parameter shift_steps = 8; parameter loadsr1=3"b001, loadsr2=3"b010, shift=3"b100; // internal variables // end else begin fsm_function = loadsr2; fsm_function = loadsr1; end input [size-1:0] state; input startstop; input index; case(state) reg index = 0; reg [size-1:0] state; wire [size-1:0] next_state; assign next_state = fsm_function(state, startstop, index); // function for states // function [size-1:0] fsm_function; endfunction. // sequential logic // always @(posedge clock) begin: fsm_seq end.
