EE 2731 Chapter : Labreport10

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15 Mar 2019
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// additional comments: module exp_10a( input clock, input w, input x, output y, output z reg [6:1] temp; parameter [6:1] a = 3"b000, b = 3"b001, c = 3"b010, d = 3"b011, e = 3"b100, f = 3"b101, g = 3"b110, h = 3"b111; initial. // define the sequential block always @(posedge clock) if (!x) temp <= a; else temp <= b; end case (temp) A: if (!w) begin else begin temp = a; H: if (!w) default: temp <= 3"bxxx; else end if (!x) temp <= f; else temp <= f; begin endmodule. // verilog test fixture created by ise for module: exp_10a. // inputs reg clock; reg w; reg x; // wait 50 ns for global reset to finish. Clock = 0; w = 0; x = 0; @(posedge clock) begin w = 1; x = 0; @(posedge clock) begin w = 0; x = 1;

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