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Chapter

# Labreport10

Department
Electrical Engineering
Course Code
EE 2731
Professor
All

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Section 3 /group 5
Experiment 10 â€“ Vending Machine Control
Digital Input(s): clock, w, x
Digital Output(s): y, z
State diagram:
Verilog:

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:34:29 04/09/2013
// Design Name:
// Module Name: Exp_10a
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_10a(
input Clock,
input w,
input x,
output y,
output z
);
reg [6:1] temp;
parameter [6:1] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100, F =
3'b101, G = 3'b110, H = 3'b111;
initial
temp = A;
// Define the sequential block
always @(posedge Clock)
case (temp)
A: if (!w)
begin
if (!x)
temp <= A;
else
temp <= B;
end
else
begin

Only pages 1-3 are available for preview. Some parts have been intentionally blurred.

if (!x)
temp <= C;
else
temp <= F;
end
B: if (!w)
begin
if (!x)
temp <= B;
else
temp <= C;
end
else
begin
if (!x)
temp <= D;
else
temp <= G;
end
C: if (!w)
begin
if (!x)
temp <= C;
else
temp <= D;
end
else
begin
if (!x)
temp <= E;
else
temp <= H;
end
D: if (!w)
begin
if (!x)
temp <= A;
else
temp <= B;
end
else
begin
if (!x)