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Chapter

Lab 6


Department
Electrical Engineering
Course Code
EE 2731
Professor
All

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Section 3 /group 5
Name of the Experiment: Programming the Diligent Spartan-3E
Board Using Xilinx ISE Design Suite
PART 1:
Digital Input(s):
A) Data inputs: X, Y, Cin
B) Select lines: none
C) Clock: none
Digital Output(s): Cout, Sum
Truth Table:
X
Y
Cin
Cout
Sum
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
Karnaugh Maps:
Cout
XY|Cin
00
01
11
0
0
0
1
1
0
1
1
Sum
XY|Cin
00
01
11
0
0
1
0
1
1
0
1

Only pages 1-3 are available for preview. Some parts have been intentionally blurred.

Equations:
Cout = XY + CinY+ CinX
Sum = X’YCin’ + XY’Cin’ + X’Y’Cin + XYCin
= X’(YCin’ + Y’Cin) + X(Y’Cin’ + YCin)
= X Y Cin
Verilog description:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:00:33 03/05/2013
// Design Name:
// Module Name: Exp_6a
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_6a(
input X,
input Y,
input Cin,
output Cout,
output Sum
);
assign Sum = X^Y^Cin;
assign Cout = (X&Y)|(X&Cin)|(Y&Cin);

Only pages 1-3 are available for preview. Some parts have been intentionally blurred.

endmodule
Test Bench:
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:03:12 03/05/2013
// Design Name: Exp_6a
// Module Name: E:/Exp_6a/Exp_6a_TB.v
// Project Name: Exp_6a
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Exp_6a
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Exp_6a_TB;
// Inputs
reg X;
reg Y;
reg Cin;
// Outputs
wire Cout;
wire Sum;
// Instantiate the Unit Under Test (UUT)
Exp_6a uut (
.X(X),
.Y(Y),
.Cin(Cin),
.Cout(Cout),
.Sum(Sum)
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