ECE 378 Quiz: ECE378 Oakland Quiz 1

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The following is the timing diagram of a logic circuit with three inputs. Simplify the boolean expression of the circuit and (january 26th @ 5:30 pm) sketch the minimized circuit. a b c f. Complete the timing diagram of the digital circuit shown below. Assume the propagation delay of every gate is 5 ns. The initial values of all signals are plotted in the figure. 1 b a c na p q f. 1 a b c na p q f.